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@@ -273,6 +273,7 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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int ret = 0;
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u32 data_delay;
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bool fs_pol_rising;
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+ bool inv_fs = false;
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pm_runtime_get_sync(mcasp->dev);
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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@@ -291,14 +292,19 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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/* No delay after FS */
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data_delay = 0;
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break;
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- default:
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+ case SND_SOC_DAIFMT_I2S:
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/* configure a full-word SYNC pulse (LRCLK) */
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mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
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mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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/* 1st data bit occur one ACLK cycle after the frame sync */
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data_delay = 1;
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+ /* FS need to be inverted */
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+ inv_fs = true;
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break;
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+ default:
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+ ret = -EINVAL;
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+ goto out;
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}
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mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
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@@ -379,6 +385,9 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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goto out;
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}
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+ if (inv_fs)
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+ fs_pol_rising = !fs_pol_rising;
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+
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if (fs_pol_rising) {
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
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