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@@ -50,6 +50,10 @@
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#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
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#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
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#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
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#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
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+#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
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+#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
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+#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
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+
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/*
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/*
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* SDRAM configuration registers.
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* SDRAM configuration registers.
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*/
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*/
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@@ -144,9 +148,9 @@
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/*
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/*
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* UART module.
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* UART module.
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*/
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*/
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-#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
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-#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
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-#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */
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+#define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */
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+#define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */
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+#define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */
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/*
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/*
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* FEC module.
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* FEC module.
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