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@@ -531,6 +531,14 @@ static inline int pcie_cap_version(const struct pci_dev *dev)
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return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
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}
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+static bool pcie_downstream_port(const struct pci_dev *dev)
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+{
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+ int type = pci_pcie_type(dev);
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+
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+ return type == PCI_EXP_TYPE_ROOT_PORT ||
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+ type == PCI_EXP_TYPE_DOWNSTREAM;
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+}
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+
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bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
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{
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int type = pci_pcie_type(dev);
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@@ -546,10 +554,7 @@ bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
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static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
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{
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- int type = pci_pcie_type(dev);
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-
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- return (type == PCI_EXP_TYPE_ROOT_PORT ||
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- type == PCI_EXP_TYPE_DOWNSTREAM) &&
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+ return pcie_downstream_port(dev) &&
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pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
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}
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@@ -628,10 +633,9 @@ int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
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* State bit in the Slot Status register of Downstream Ports,
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* which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
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*/
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- if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
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- pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
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+ if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
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+ pos == PCI_EXP_SLTSTA)
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*val = PCI_EXP_SLTSTA_PDS;
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- }
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return 0;
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}
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@@ -657,10 +661,9 @@ int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
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return ret;
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}
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- if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
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- pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
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+ if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
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+ pos == PCI_EXP_SLTSTA)
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*val = PCI_EXP_SLTSTA_PDS;
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- }
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return 0;
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}
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