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@@ -17,6 +17,18 @@
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};
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};
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+ mailbox: mhu@2b1f0000 {
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+ compatible = "arm,mhu", "arm,primecell";
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+ reg = <0x0 0x2b1f0000 0x0 0x1000>;
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+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "mhu_lpri_rx",
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+ "mhu_hpri_rx";
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+ #mbox-cells = <1>;
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+ clocks = <&soc_refclk100mhz>;
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+ clock-names = "apb_pclk";
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+ };
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+
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gic: interrupt-controller@2c010000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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reg = <0x0 0x2c010000 0 0x1000>,
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@@ -44,6 +56,48 @@
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
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};
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+ sram: sram@2e000000 {
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+ compatible = "arm,juno-sram-ns", "mmio-sram";
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+ reg = <0x0 0x2e000000 0x0 0x8000>;
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+
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0x0 0x2e000000 0x8000>;
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+
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+ cpu_scp_lpri: scp-shmem@0 {
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+ compatible = "arm,juno-scp-shmem";
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+ reg = <0x0 0x200>;
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+ };
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+
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+ cpu_scp_hpri: scp-shmem@200 {
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+ compatible = "arm,juno-scp-shmem";
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+ reg = <0x200 0x200>;
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+ };
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+ };
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+
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+ scpi {
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+ compatible = "arm,scpi";
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+ mboxes = <&mailbox 1>;
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+ shmem = <&cpu_scp_hpri>;
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+
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+ clocks {
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+ compatible = "arm,scpi-clocks";
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+
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+ scpi_dvfs: scpi_clocks@0 {
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+ compatible = "arm,scpi-dvfs-clocks";
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+ #clock-cells = <1>;
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+ clock-indices = <0>, <1>, <2>;
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+ clock-output-names = "atlclk", "aplclk","gpuclk";
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+ };
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+ scpi_clk: scpi_clocks@3 {
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+ compatible = "arm,scpi-variable-clocks";
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+ #clock-cells = <1>;
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+ clock-indices = <3>, <4>;
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+ clock-output-names = "pxlclk0", "pxlclk1";
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+ };
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+ };
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+ };
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+
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/include/ "juno-clocks.dtsi"
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dma@7ff00000 {
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