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@@ -58,6 +58,7 @@ Table of Contents
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o) Xilinx IP cores
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p) Freescale Synchronous Serial Interface
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q) USB EHCI controllers
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+ r) MDIO on GPIOs
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VII - Marvell Discovery mv64[345]6x System Controller chips
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1) The /system-controller node
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@@ -88,10 +89,12 @@ Table of Contents
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3) OpenPIC Interrupt Controllers
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4) ISA Interrupt Controllers
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- VIII - Specifying GPIO information for devices
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+ IX - Specifying GPIO information for devices
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1) gpios property
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2) gpio-controller nodes
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+ X - Specifying device power management information (sleep property)
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+
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Appendix A - Sample SOC node for MPC8540
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@@ -1246,80 +1249,7 @@ descriptions for the SOC devices for which new nodes have been
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defined; this list will expand as more and more SOC-containing
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platforms are moved over to use the flattened-device-tree model.
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- a) MDIO IO device
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-
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- The MDIO is a bus to which the PHY devices are connected. For each
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- device that exists on this bus, a child node should be created. See
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- the definition of the PHY node below for an example of how to define
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- a PHY.
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-
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- Required properties:
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- - reg : Offset and length of the register set for the device
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- - compatible : Should define the compatible device type for the
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- mdio. Currently, this is most likely to be "fsl,gianfar-mdio"
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-
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- Example:
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-
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- mdio@24520 {
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- reg = <24520 20>;
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- compatible = "fsl,gianfar-mdio";
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-
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- ethernet-phy@0 {
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- ......
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- };
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- };
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-
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-
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- b) Gianfar-compatible ethernet nodes
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-
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- Required properties:
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-
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- - device_type : Should be "network"
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- - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
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- - compatible : Should be "gianfar"
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- - reg : Offset and length of the register set for the device
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- - mac-address : List of bytes representing the ethernet address of
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- this controller
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- - interrupts : <a b> where a is the interrupt number and b is a
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- field that represents an encoding of the sense and level
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- information for the interrupt. This should be encoded based on
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- the information in section 2) depending on the type of interrupt
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- controller you have.
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- - interrupt-parent : the phandle for the interrupt controller that
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- services interrupts for this device.
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- - phy-handle : The phandle for the PHY connected to this ethernet
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- controller.
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- - fixed-link : <a b c d e> where a is emulated phy id - choose any,
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- but unique to the all specified fixed-links, b is duplex - 0 half,
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- 1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
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- pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
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-
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- Recommended properties:
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-
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- - phy-connection-type : a string naming the controller/PHY interface type,
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- i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
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- "tbi", or "rtbi". This property is only really needed if the connection
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- is of type "rgmii-id", as all other connection types are detected by
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- hardware.
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-
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-
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- Example:
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-
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- ethernet@24000 {
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- #size-cells = <0>;
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- device_type = "network";
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- model = "TSEC";
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- compatible = "gianfar";
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- reg = <24000 1000>;
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- mac-address = [ 00 E0 0C 00 73 00 ];
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- interrupts = <d 3 e 3 12 3>;
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- interrupt-parent = <40000>;
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- phy-handle = <2452000>
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- };
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-
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-
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-
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- c) PHY nodes
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+ a) PHY nodes
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Required properties:
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@@ -1347,7 +1277,7 @@ platforms are moved over to use the flattened-device-tree model.
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};
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- d) Interrupt controllers
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+ b) Interrupt controllers
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Some SOC devices contain interrupt controllers that are different
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from the standard Open PIC specification. The SOC device nodes for
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@@ -1360,491 +1290,14 @@ platforms are moved over to use the flattened-device-tree model.
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pic@40000 {
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linux,phandle = <40000>;
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- clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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reg = <40000 40000>;
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- built-in;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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- big-endian;
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- };
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-
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-
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- e) I2C
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-
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- Required properties :
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-
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- - device_type : Should be "i2c"
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- - reg : Offset and length of the register set for the device
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-
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- Recommended properties :
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-
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- - compatible : Should be "fsl-i2c" for parts compatible with
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- Freescale I2C specifications.
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- - interrupts : <a b> where a is the interrupt number and b is a
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- field that represents an encoding of the sense and level
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- information for the interrupt. This should be encoded based on
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- the information in section 2) depending on the type of interrupt
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- controller you have.
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- - interrupt-parent : the phandle for the interrupt controller that
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- services interrupts for this device.
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- - dfsrr : boolean; if defined, indicates that this I2C device has
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- a digital filter sampling rate register
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- - fsl5200-clocking : boolean; if defined, indicated that this device
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- uses the FSL 5200 clocking mechanism.
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-
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- Example :
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-
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- i2c@3000 {
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- interrupt-parent = <40000>;
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- interrupts = <1b 3>;
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- reg = <3000 18>;
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- device_type = "i2c";
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- compatible = "fsl-i2c";
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- dfsrr;
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- };
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-
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-
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- f) Freescale SOC USB controllers
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-
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- The device node for a USB controller that is part of a Freescale
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- SOC is as described in the document "Open Firmware Recommended
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- Practice : Universal Serial Bus" with the following modifications
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- and additions :
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-
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- Required properties :
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- - compatible : Should be "fsl-usb2-mph" for multi port host USB
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- controllers, or "fsl-usb2-dr" for dual role USB controllers
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- - phy_type : For multi port host USB controllers, should be one of
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- "ulpi", or "serial". For dual role USB controllers, should be
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- one of "ulpi", "utmi", "utmi_wide", or "serial".
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- - reg : Offset and length of the register set for the device
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- - port0 : boolean; if defined, indicates port0 is connected for
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- fsl-usb2-mph compatible controllers. Either this property or
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- "port1" (or both) must be defined for "fsl-usb2-mph" compatible
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- controllers.
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- - port1 : boolean; if defined, indicates port1 is connected for
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- fsl-usb2-mph compatible controllers. Either this property or
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- "port0" (or both) must be defined for "fsl-usb2-mph" compatible
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- controllers.
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- - dr_mode : indicates the working mode for "fsl-usb2-dr" compatible
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- controllers. Can be "host", "peripheral", or "otg". Default to
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- "host" if not defined for backward compatibility.
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-
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- Recommended properties :
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- - interrupts : <a b> where a is the interrupt number and b is a
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- field that represents an encoding of the sense and level
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- information for the interrupt. This should be encoded based on
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- the information in section 2) depending on the type of interrupt
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- controller you have.
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- - interrupt-parent : the phandle for the interrupt controller that
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- services interrupts for this device.
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-
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- Example multi port host USB controller device node :
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- usb@22000 {
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- compatible = "fsl-usb2-mph";
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- reg = <22000 1000>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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- interrupt-parent = <700>;
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- interrupts = <27 1>;
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- phy_type = "ulpi";
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- port0;
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- port1;
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- };
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-
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- Example dual role USB controller device node :
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- usb@23000 {
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- compatible = "fsl-usb2-dr";
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- reg = <23000 1000>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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- interrupt-parent = <700>;
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- interrupts = <26 1>;
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- dr_mode = "otg";
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- phy = "ulpi";
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- };
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-
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-
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- g) Freescale SOC SEC Security Engines
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-
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- Required properties:
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-
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- - device_type : Should be "crypto"
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- - model : Model of the device. Should be "SEC1" or "SEC2"
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- - compatible : Should be "talitos"
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- - reg : Offset and length of the register set for the device
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- - interrupts : <a b> where a is the interrupt number and b is a
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- field that represents an encoding of the sense and level
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- information for the interrupt. This should be encoded based on
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- the information in section 2) depending on the type of interrupt
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- controller you have.
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- - interrupt-parent : the phandle for the interrupt controller that
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- services interrupts for this device.
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- - num-channels : An integer representing the number of channels
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- available.
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- - channel-fifo-len : An integer representing the number of
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- descriptor pointers each channel fetch fifo can hold.
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- - exec-units-mask : The bitmask representing what execution units
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- (EUs) are available. It's a single 32-bit cell. EU information
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- should be encoded following the SEC's Descriptor Header Dword
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- EU_SEL0 field documentation, i.e. as follows:
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-
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- bit 0 = reserved - should be 0
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- bit 1 = set if SEC has the ARC4 EU (AFEU)
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- bit 2 = set if SEC has the DES/3DES EU (DEU)
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- bit 3 = set if SEC has the message digest EU (MDEU)
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- bit 4 = set if SEC has the random number generator EU (RNG)
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- bit 5 = set if SEC has the public key EU (PKEU)
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- bit 6 = set if SEC has the AES EU (AESU)
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- bit 7 = set if SEC has the Kasumi EU (KEU)
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-
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- bits 8 through 31 are reserved for future SEC EUs.
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-
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- - descriptor-types-mask : The bitmask representing what descriptors
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- are available. It's a single 32-bit cell. Descriptor type
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- information should be encoded following the SEC's Descriptor
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- Header Dword DESC_TYPE field documentation, i.e. as follows:
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-
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- bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
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- bit 1 = set if SEC supports the ipsec_esp descriptor type
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- bit 2 = set if SEC supports the common_nonsnoop desc. type
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- bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
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- bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
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- bit 5 = set if SEC supports the srtp descriptor type
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- bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
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- bit 7 = set if SEC supports the pkeu_assemble descriptor type
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- bit 8 = set if SEC supports the aesu_key_expand_output desc.type
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- bit 9 = set if SEC supports the pkeu_ptmul descriptor type
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- bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
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- bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
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-
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- ..and so on and so forth.
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-
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- Example:
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-
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- /* MPC8548E */
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- crypto@30000 {
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- device_type = "crypto";
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- model = "SEC2";
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- compatible = "talitos";
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- reg = <30000 10000>;
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- interrupts = <1d 3>;
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- interrupt-parent = <40000>;
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- num-channels = <4>;
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- channel-fifo-len = <18>;
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- exec-units-mask = <000000fe>;
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- descriptor-types-mask = <012b0ebf>;
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- };
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-
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- h) Board Control and Status (BCSR)
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-
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- Required properties:
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-
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- - device_type : Should be "board-control"
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- - reg : Offset and length of the register set for the device
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-
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- Example:
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-
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- bcsr@f8000000 {
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- device_type = "board-control";
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- reg = <f8000000 8000>;
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};
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- i) Freescale QUICC Engine module (QE)
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- This represents qe module that is installed on PowerQUICC II Pro.
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-
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- NOTE: This is an interim binding; it should be updated to fit
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- in with the CPM binding later in this document.
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-
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- Basically, it is a bus of devices, that could act more or less
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- as a complete entity (UCC, USB etc ). All of them should be siblings on
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- the "root" qe node, using the common properties from there.
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- The description below applies to the qe of MPC8360 and
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- more nodes and properties would be extended in the future.
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-
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- i) Root QE device
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-
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- Required properties:
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- - compatible : should be "fsl,qe";
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- - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
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- - reg : offset and length of the device registers.
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- - bus-frequency : the clock frequency for QUICC Engine.
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-
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- Recommended properties
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- - brg-frequency : the internal clock source frequency for baud-rate
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- generators in Hz.
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-
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- Example:
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- qe@e0100000 {
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- #address-cells = <1>;
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- #size-cells = <1>;
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- #interrupt-cells = <2>;
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- compatible = "fsl,qe";
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- ranges = <0 e0100000 00100000>;
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- reg = <e0100000 480>;
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- brg-frequency = <0>;
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- bus-frequency = <179A7B00>;
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- }
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-
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-
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- ii) SPI (Serial Peripheral Interface)
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-
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- Required properties:
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- - cell-index : SPI controller index.
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- - compatible : should be "fsl,spi".
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- - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
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- - reg : Offset and length of the register set for the device
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- - interrupts : <a b> where a is the interrupt number and b is a
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- field that represents an encoding of the sense and level
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- information for the interrupt. This should be encoded based on
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- the information in section 2) depending on the type of interrupt
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- controller you have.
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- - interrupt-parent : the phandle for the interrupt controller that
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- services interrupts for this device.
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-
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- Example:
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- spi@4c0 {
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- cell-index = <0>;
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- compatible = "fsl,spi";
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- reg = <4c0 40>;
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- interrupts = <82 0>;
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- interrupt-parent = <700>;
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- mode = "cpu";
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- };
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-
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-
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- iii) USB (Universal Serial Bus Controller)
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-
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- Required properties:
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- - compatible : could be "qe_udc" or "fhci-hcd".
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- - mode : the could be "host" or "slave".
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- - reg : Offset and length of the register set for the device
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- - interrupts : <a b> where a is the interrupt number and b is a
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- field that represents an encoding of the sense and level
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- information for the interrupt. This should be encoded based on
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- the information in section 2) depending on the type of interrupt
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- controller you have.
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- - interrupt-parent : the phandle for the interrupt controller that
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- services interrupts for this device.
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-
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- Example(slave):
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- usb@6c0 {
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- compatible = "qe_udc";
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- reg = <6c0 40>;
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- interrupts = <8b 0>;
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- interrupt-parent = <700>;
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- mode = "slave";
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- };
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-
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-
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- iv) UCC (Unified Communications Controllers)
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-
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- Required properties:
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- - device_type : should be "network", "hldc", "uart", "transparent"
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- "bisync", "atm", or "serial".
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- - compatible : could be "ucc_geth" or "fsl_atm" and so on.
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- - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
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- - reg : Offset and length of the register set for the device
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- - interrupts : <a b> where a is the interrupt number and b is a
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- field that represents an encoding of the sense and level
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- information for the interrupt. This should be encoded based on
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|
|
- the information in section 2) depending on the type of interrupt
|
|
|
- controller you have.
|
|
|
- - interrupt-parent : the phandle for the interrupt controller that
|
|
|
- services interrupts for this device.
|
|
|
- - pio-handle : The phandle for the Parallel I/O port configuration.
|
|
|
- - port-number : for UART drivers, the port number to use, between 0 and 3.
|
|
|
- This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
|
|
|
- The port number is added to the minor number of the device. Unlike the
|
|
|
- CPM UART driver, the port-number is required for the QE UART driver.
|
|
|
- - soft-uart : for UART drivers, if specified this means the QE UART device
|
|
|
- driver should use "Soft-UART" mode, which is needed on some SOCs that have
|
|
|
- broken UART hardware. Soft-UART is provided via a microcode upload.
|
|
|
- - rx-clock-name: the UCC receive clock source
|
|
|
- "none": clock source is disabled
|
|
|
- "brg1" through "brg16": clock source is BRG1-BRG16, respectively
|
|
|
- "clk1" through "clk24": clock source is CLK1-CLK24, respectively
|
|
|
- - tx-clock-name: the UCC transmit clock source
|
|
|
- "none": clock source is disabled
|
|
|
- "brg1" through "brg16": clock source is BRG1-BRG16, respectively
|
|
|
- "clk1" through "clk24": clock source is CLK1-CLK24, respectively
|
|
|
- The following two properties are deprecated. rx-clock has been replaced
|
|
|
- with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
|
|
|
- Drivers that currently use the deprecated properties should continue to
|
|
|
- do so, in order to support older device trees, but they should be updated
|
|
|
- to check for the new properties first.
|
|
|
- - rx-clock : represents the UCC receive clock source.
|
|
|
- 0x00 : clock source is disabled;
|
|
|
- 0x1~0x10 : clock source is BRG1~BRG16 respectively;
|
|
|
- 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
|
|
|
- - tx-clock: represents the UCC transmit clock source;
|
|
|
- 0x00 : clock source is disabled;
|
|
|
- 0x1~0x10 : clock source is BRG1~BRG16 respectively;
|
|
|
- 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
|
|
|
-
|
|
|
- Required properties for network device_type:
|
|
|
- - mac-address : list of bytes representing the ethernet address.
|
|
|
- - phy-handle : The phandle for the PHY connected to this controller.
|
|
|
-
|
|
|
- Recommended properties:
|
|
|
- - phy-connection-type : a string naming the controller/PHY interface type,
|
|
|
- i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
|
|
|
- Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
|
|
|
- "tbi", or "rtbi".
|
|
|
-
|
|
|
- Example:
|
|
|
- ucc@2000 {
|
|
|
- device_type = "network";
|
|
|
- compatible = "ucc_geth";
|
|
|
- cell-index = <1>;
|
|
|
- reg = <2000 200>;
|
|
|
- interrupts = <a0 0>;
|
|
|
- interrupt-parent = <700>;
|
|
|
- mac-address = [ 00 04 9f 00 23 23 ];
|
|
|
- rx-clock = "none";
|
|
|
- tx-clock = "clk9";
|
|
|
- phy-handle = <212000>;
|
|
|
- phy-connection-type = "gmii";
|
|
|
- pio-handle = <140001>;
|
|
|
- };
|
|
|
-
|
|
|
-
|
|
|
- v) Parallel I/O Ports
|
|
|
-
|
|
|
- This node configures Parallel I/O ports for CPUs with QE support.
|
|
|
- The node should reside in the "soc" node of the tree. For each
|
|
|
- device that using parallel I/O ports, a child node should be created.
|
|
|
- See the definition of the Pin configuration nodes below for more
|
|
|
- information.
|
|
|
-
|
|
|
- Required properties:
|
|
|
- - device_type : should be "par_io".
|
|
|
- - reg : offset to the register set and its length.
|
|
|
- - num-ports : number of Parallel I/O ports
|
|
|
-
|
|
|
- Example:
|
|
|
- par_io@1400 {
|
|
|
- reg = <1400 100>;
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <0>;
|
|
|
- device_type = "par_io";
|
|
|
- num-ports = <7>;
|
|
|
- ucc_pin@01 {
|
|
|
- ......
|
|
|
- };
|
|
|
-
|
|
|
-
|
|
|
- vi) Pin configuration nodes
|
|
|
-
|
|
|
- Required properties:
|
|
|
- - linux,phandle : phandle of this node; likely referenced by a QE
|
|
|
- device.
|
|
|
- - pio-map : array of pin configurations. Each pin is defined by 6
|
|
|
- integers. The six numbers are respectively: port, pin, dir,
|
|
|
- open_drain, assignment, has_irq.
|
|
|
- - port : port number of the pin; 0-6 represent port A-G in UM.
|
|
|
- - pin : pin number in the port.
|
|
|
- - dir : direction of the pin, should encode as follows:
|
|
|
-
|
|
|
- 0 = The pin is disabled
|
|
|
- 1 = The pin is an output
|
|
|
- 2 = The pin is an input
|
|
|
- 3 = The pin is I/O
|
|
|
-
|
|
|
- - open_drain : indicates the pin is normal or wired-OR:
|
|
|
-
|
|
|
- 0 = The pin is actively driven as an output
|
|
|
- 1 = The pin is an open-drain driver. As an output, the pin is
|
|
|
- driven active-low, otherwise it is three-stated.
|
|
|
-
|
|
|
- - assignment : function number of the pin according to the Pin Assignment
|
|
|
- tables in User Manual. Each pin can have up to 4 possible functions in
|
|
|
- QE and two options for CPM.
|
|
|
- - has_irq : indicates if the pin is used as source of external
|
|
|
- interrupts.
|
|
|
-
|
|
|
- Example:
|
|
|
- ucc_pin@01 {
|
|
|
- linux,phandle = <140001>;
|
|
|
- pio-map = <
|
|
|
- /* port pin dir open_drain assignment has_irq */
|
|
|
- 0 3 1 0 1 0 /* TxD0 */
|
|
|
- 0 4 1 0 1 0 /* TxD1 */
|
|
|
- 0 5 1 0 1 0 /* TxD2 */
|
|
|
- 0 6 1 0 1 0 /* TxD3 */
|
|
|
- 1 6 1 0 3 0 /* TxD4 */
|
|
|
- 1 7 1 0 1 0 /* TxD5 */
|
|
|
- 1 9 1 0 2 0 /* TxD6 */
|
|
|
- 1 a 1 0 2 0 /* TxD7 */
|
|
|
- 0 9 2 0 1 0 /* RxD0 */
|
|
|
- 0 a 2 0 1 0 /* RxD1 */
|
|
|
- 0 b 2 0 1 0 /* RxD2 */
|
|
|
- 0 c 2 0 1 0 /* RxD3 */
|
|
|
- 0 d 2 0 1 0 /* RxD4 */
|
|
|
- 1 1 2 0 2 0 /* RxD5 */
|
|
|
- 1 0 2 0 2 0 /* RxD6 */
|
|
|
- 1 4 2 0 2 0 /* RxD7 */
|
|
|
- 0 7 1 0 1 0 /* TX_EN */
|
|
|
- 0 8 1 0 1 0 /* TX_ER */
|
|
|
- 0 f 2 0 1 0 /* RX_DV */
|
|
|
- 0 10 2 0 1 0 /* RX_ER */
|
|
|
- 0 0 2 0 1 0 /* RX_CLK */
|
|
|
- 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
|
|
|
- 2 8 2 0 1 0>; /* GTX125 - CLK9 */
|
|
|
- };
|
|
|
-
|
|
|
- vii) Multi-User RAM (MURAM)
|
|
|
-
|
|
|
- Required properties:
|
|
|
- - compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
|
|
|
- - mode : the could be "host" or "slave".
|
|
|
- - ranges : Should be defined as specified in 1) to describe the
|
|
|
- translation of MURAM addresses.
|
|
|
- - data-only : sub-node which defines the address area under MURAM
|
|
|
- bus that can be allocated as data/parameter
|
|
|
-
|
|
|
- Example:
|
|
|
-
|
|
|
- muram@10000 {
|
|
|
- compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
|
|
- ranges = <0 00010000 0000c000>;
|
|
|
-
|
|
|
- data-only@0{
|
|
|
- compatible = "fsl,qe-muram-data",
|
|
|
- "fsl,cpm-muram-data";
|
|
|
- reg = <0 c000>;
|
|
|
- };
|
|
|
- };
|
|
|
-
|
|
|
- viii) Uploaded QE firmware
|
|
|
-
|
|
|
- If a new firwmare has been uploaded to the QE (usually by the
|
|
|
- boot loader), then a 'firmware' child node should be added to the QE
|
|
|
- node. This node provides information on the uploaded firmware that
|
|
|
- device drivers may need.
|
|
|
-
|
|
|
- Required properties:
|
|
|
- - id: The string name of the firmware. This is taken from the 'id'
|
|
|
- member of the qe_firmware structure of the uploaded firmware.
|
|
|
- Device drivers can search this string to determine if the
|
|
|
- firmware they want is already present.
|
|
|
- - extended-modes: The Extended Modes bitfield, taken from the
|
|
|
- firmware binary. It is a 64-bit number represented
|
|
|
- as an array of two 32-bit numbers.
|
|
|
- - virtual-traps: The virtual traps, taken from the firmware binary.
|
|
|
- It is an array of 8 32-bit numbers.
|
|
|
-
|
|
|
- Example:
|
|
|
-
|
|
|
- firmware {
|
|
|
- id = "Soft-UART";
|
|
|
- extended-modes = <0 0>;
|
|
|
- virtual-traps = <0 0 0 0 0 0 0 0>;
|
|
|
- }
|
|
|
-
|
|
|
- j) CFI or JEDEC memory-mapped NOR flash
|
|
|
+ c) CFI or JEDEC memory-mapped NOR flash
|
|
|
|
|
|
Flash chips (Memory Technology Devices) are often used for solid state
|
|
|
file systems on embedded devices.
|
|
@@ -1908,268 +1361,7 @@ platforms are moved over to use the flattened-device-tree model.
|
|
|
};
|
|
|
};
|
|
|
|
|
|
- k) Global Utilities Block
|
|
|
-
|
|
|
- The global utilities block controls power management, I/O device
|
|
|
- enabling, power-on-reset configuration monitoring, general-purpose
|
|
|
- I/O signal configuration, alternate function selection for multiplexed
|
|
|
- signals, and clock control.
|
|
|
-
|
|
|
- Required properties:
|
|
|
-
|
|
|
- - compatible : Should define the compatible device type for
|
|
|
- global-utilities.
|
|
|
- - reg : Offset and length of the register set for the device.
|
|
|
-
|
|
|
- Recommended properties:
|
|
|
-
|
|
|
- - fsl,has-rstcr : Indicates that the global utilities register set
|
|
|
- contains a functioning "reset control register" (i.e. the board
|
|
|
- is wired to reset upon setting the HRESET_REQ bit in this register).
|
|
|
-
|
|
|
- Example:
|
|
|
-
|
|
|
- global-utilities@e0000 { /* global utilities block */
|
|
|
- compatible = "fsl,mpc8548-guts";
|
|
|
- reg = <e0000 1000>;
|
|
|
- fsl,has-rstcr;
|
|
|
- };
|
|
|
-
|
|
|
- l) Freescale Communications Processor Module
|
|
|
-
|
|
|
- NOTE: This is an interim binding, and will likely change slightly,
|
|
|
- as more devices are supported. The QE bindings especially are
|
|
|
- incomplete.
|
|
|
-
|
|
|
- i) Root CPM node
|
|
|
-
|
|
|
- Properties:
|
|
|
- - compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
|
|
|
- - reg : A 48-byte region beginning with CPCR.
|
|
|
-
|
|
|
- Example:
|
|
|
- cpm@119c0 {
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <1>;
|
|
|
- #interrupt-cells = <2>;
|
|
|
- compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
|
|
|
- reg = <119c0 30>;
|
|
|
- }
|
|
|
-
|
|
|
- ii) Properties common to mulitple CPM/QE devices
|
|
|
-
|
|
|
- - fsl,cpm-command : This value is ORed with the opcode and command flag
|
|
|
- to specify the device on which a CPM command operates.
|
|
|
-
|
|
|
- - fsl,cpm-brg : Indicates which baud rate generator the device
|
|
|
- is associated with. If absent, an unused BRG
|
|
|
- should be dynamically allocated. If zero, the
|
|
|
- device uses an external clock rather than a BRG.
|
|
|
-
|
|
|
- - reg : Unless otherwise specified, the first resource represents the
|
|
|
- scc/fcc/ucc registers, and the second represents the device's
|
|
|
- parameter RAM region (if it has one).
|
|
|
-
|
|
|
- iii) Serial
|
|
|
-
|
|
|
- Currently defined compatibles:
|
|
|
- - fsl,cpm1-smc-uart
|
|
|
- - fsl,cpm2-smc-uart
|
|
|
- - fsl,cpm1-scc-uart
|
|
|
- - fsl,cpm2-scc-uart
|
|
|
- - fsl,qe-uart
|
|
|
-
|
|
|
- Example:
|
|
|
-
|
|
|
- serial@11a00 {
|
|
|
- device_type = "serial";
|
|
|
- compatible = "fsl,mpc8272-scc-uart",
|
|
|
- "fsl,cpm2-scc-uart";
|
|
|
- reg = <11a00 20 8000 100>;
|
|
|
- interrupts = <28 8>;
|
|
|
- interrupt-parent = <&PIC>;
|
|
|
- fsl,cpm-brg = <1>;
|
|
|
- fsl,cpm-command = <00800000>;
|
|
|
- };
|
|
|
-
|
|
|
- iii) Network
|
|
|
-
|
|
|
- Currently defined compatibles:
|
|
|
- - fsl,cpm1-scc-enet
|
|
|
- - fsl,cpm2-scc-enet
|
|
|
- - fsl,cpm1-fec-enet
|
|
|
- - fsl,cpm2-fcc-enet (third resource is GFEMR)
|
|
|
- - fsl,qe-enet
|
|
|
-
|
|
|
- Example:
|
|
|
-
|
|
|
- ethernet@11300 {
|
|
|
- device_type = "network";
|
|
|
- compatible = "fsl,mpc8272-fcc-enet",
|
|
|
- "fsl,cpm2-fcc-enet";
|
|
|
- reg = <11300 20 8400 100 11390 1>;
|
|
|
- local-mac-address = [ 00 00 00 00 00 00 ];
|
|
|
- interrupts = <20 8>;
|
|
|
- interrupt-parent = <&PIC>;
|
|
|
- phy-handle = <&PHY0>;
|
|
|
- fsl,cpm-command = <12000300>;
|
|
|
- };
|
|
|
-
|
|
|
- iv) MDIO
|
|
|
-
|
|
|
- Currently defined compatibles:
|
|
|
- fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
|
|
|
- fsl,cpm2-mdio-bitbang (reg is port C registers)
|
|
|
-
|
|
|
- Properties for fsl,cpm2-mdio-bitbang:
|
|
|
- fsl,mdio-pin : pin of port C controlling mdio data
|
|
|
- fsl,mdc-pin : pin of port C controlling mdio clock
|
|
|
-
|
|
|
- Example:
|
|
|
-
|
|
|
- mdio@10d40 {
|
|
|
- device_type = "mdio";
|
|
|
- compatible = "fsl,mpc8272ads-mdio-bitbang",
|
|
|
- "fsl,mpc8272-mdio-bitbang",
|
|
|
- "fsl,cpm2-mdio-bitbang";
|
|
|
- reg = <10d40 14>;
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <0>;
|
|
|
- fsl,mdio-pin = <12>;
|
|
|
- fsl,mdc-pin = <13>;
|
|
|
- };
|
|
|
-
|
|
|
- v) Baud Rate Generators
|
|
|
-
|
|
|
- Currently defined compatibles:
|
|
|
- fsl,cpm-brg
|
|
|
- fsl,cpm1-brg
|
|
|
- fsl,cpm2-brg
|
|
|
-
|
|
|
- Properties:
|
|
|
- - reg : There may be an arbitrary number of reg resources; BRG
|
|
|
- numbers are assigned to these in order.
|
|
|
- - clock-frequency : Specifies the base frequency driving
|
|
|
- the BRG.
|
|
|
-
|
|
|
- Example:
|
|
|
-
|
|
|
- brg@119f0 {
|
|
|
- compatible = "fsl,mpc8272-brg",
|
|
|
- "fsl,cpm2-brg",
|
|
|
- "fsl,cpm-brg";
|
|
|
- reg = <119f0 10 115f0 10>;
|
|
|
- clock-frequency = <d#25000000>;
|
|
|
- };
|
|
|
-
|
|
|
- vi) Interrupt Controllers
|
|
|
-
|
|
|
- Currently defined compatibles:
|
|
|
- - fsl,cpm1-pic
|
|
|
- - only one interrupt cell
|
|
|
- - fsl,pq1-pic
|
|
|
- - fsl,cpm2-pic
|
|
|
- - second interrupt cell is level/sense:
|
|
|
- - 2 is falling edge
|
|
|
- - 8 is active low
|
|
|
-
|
|
|
- Example:
|
|
|
-
|
|
|
- interrupt-controller@10c00 {
|
|
|
- #interrupt-cells = <2>;
|
|
|
- interrupt-controller;
|
|
|
- reg = <10c00 80>;
|
|
|
- compatible = "mpc8272-pic", "fsl,cpm2-pic";
|
|
|
- };
|
|
|
-
|
|
|
- vii) USB (Universal Serial Bus Controller)
|
|
|
-
|
|
|
- Properties:
|
|
|
- - compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
|
|
|
-
|
|
|
- Example:
|
|
|
- usb@11bc0 {
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <0>;
|
|
|
- compatible = "fsl,cpm2-usb";
|
|
|
- reg = <11b60 18 8b00 100>;
|
|
|
- interrupts = <b 8>;
|
|
|
- interrupt-parent = <&PIC>;
|
|
|
- fsl,cpm-command = <2e600000>;
|
|
|
- };
|
|
|
-
|
|
|
- viii) Multi-User RAM (MURAM)
|
|
|
-
|
|
|
- The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
|
|
|
-
|
|
|
- Ranges must be set up subject to the following restrictions:
|
|
|
-
|
|
|
- - Children's reg nodes must be offsets from the start of all muram, even
|
|
|
- if the user-data area does not begin at zero.
|
|
|
- - If multiple range entries are used, the difference between the parent
|
|
|
- address and the child address must be the same in all, so that a single
|
|
|
- mapping can cover them all while maintaining the ability to determine
|
|
|
- CPM-side offsets with pointer subtraction. It is recommended that
|
|
|
- multiple range entries not be used.
|
|
|
- - A child address of zero must be translatable, even if no reg resources
|
|
|
- contain it.
|
|
|
-
|
|
|
- A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
|
|
|
- indicate the portion of muram that is usable by the OS for arbitrary
|
|
|
- purposes. The data node may have an arbitrary number of reg resources,
|
|
|
- all of which contribute to the allocatable muram pool.
|
|
|
-
|
|
|
- Example, based on mpc8272:
|
|
|
-
|
|
|
- muram@0 {
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <1>;
|
|
|
- ranges = <0 0 10000>;
|
|
|
-
|
|
|
- data@0 {
|
|
|
- compatible = "fsl,cpm-muram-data";
|
|
|
- reg = <0 2000 9800 800>;
|
|
|
- };
|
|
|
- };
|
|
|
-
|
|
|
- m) Chipselect/Local Bus
|
|
|
-
|
|
|
- Properties:
|
|
|
- - name : Should be localbus
|
|
|
- - #address-cells : Should be either two or three. The first cell is the
|
|
|
- chipselect number, and the remaining cells are the
|
|
|
- offset into the chipselect.
|
|
|
- - #size-cells : Either one or two, depending on how large each chipselect
|
|
|
- can be.
|
|
|
- - ranges : Each range corresponds to a single chipselect, and cover
|
|
|
- the entire access window as configured.
|
|
|
-
|
|
|
- Example:
|
|
|
- localbus@f0010100 {
|
|
|
- compatible = "fsl,mpc8272-localbus",
|
|
|
- "fsl,pq2-localbus";
|
|
|
- #address-cells = <2>;
|
|
|
- #size-cells = <1>;
|
|
|
- reg = <f0010100 40>;
|
|
|
-
|
|
|
- ranges = <0 0 fe000000 02000000
|
|
|
- 1 0 f4500000 00008000>;
|
|
|
-
|
|
|
- flash@0,0 {
|
|
|
- compatible = "jedec-flash";
|
|
|
- reg = <0 0 2000000>;
|
|
|
- bank-width = <4>;
|
|
|
- device-width = <1>;
|
|
|
- };
|
|
|
-
|
|
|
- board-control@1,0 {
|
|
|
- reg = <1 0 20>;
|
|
|
- compatible = "fsl,mpc8272ads-bcsr";
|
|
|
- };
|
|
|
- };
|
|
|
-
|
|
|
-
|
|
|
- n) 4xx/Axon EMAC ethernet nodes
|
|
|
+ d) 4xx/Axon EMAC ethernet nodes
|
|
|
|
|
|
The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
|
|
|
the Axon bridge. To operate this needs to interact with a ths
|
|
@@ -2317,7 +1509,7 @@ platforms are moved over to use the flattened-device-tree model.
|
|
|
available.
|
|
|
For Axon: 0x0000012a
|
|
|
|
|
|
- o) Xilinx IP cores
|
|
|
+ e) Xilinx IP cores
|
|
|
|
|
|
The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
|
|
|
in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
|
|
@@ -2611,206 +1803,7 @@ platforms are moved over to use the flattened-device-tree model.
|
|
|
- reg-offset : A value of 3 is required
|
|
|
- reg-shift : A value of 2 is required
|
|
|
|
|
|
-
|
|
|
- p) Freescale Synchronous Serial Interface
|
|
|
-
|
|
|
- The SSI is a serial device that communicates with audio codecs. It can
|
|
|
- be programmed in AC97, I2S, left-justified, or right-justified modes.
|
|
|
-
|
|
|
- Required properties:
|
|
|
- - compatible : compatible list, containing "fsl,ssi"
|
|
|
- - cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on
|
|
|
- - reg : offset and length of the register set for the device
|
|
|
- - interrupts : <a b> where a is the interrupt number and b is a
|
|
|
- field that represents an encoding of the sense and
|
|
|
- level information for the interrupt. This should be
|
|
|
- encoded based on the information in section 2)
|
|
|
- depending on the type of interrupt controller you
|
|
|
- have.
|
|
|
- - interrupt-parent : the phandle for the interrupt controller that
|
|
|
- services interrupts for this device.
|
|
|
- - fsl,mode : the operating mode for the SSI interface
|
|
|
- "i2s-slave" - I2S mode, SSI is clock slave
|
|
|
- "i2s-master" - I2S mode, SSI is clock master
|
|
|
- "lj-slave" - left-justified mode, SSI is clock slave
|
|
|
- "lj-master" - l.j. mode, SSI is clock master
|
|
|
- "rj-slave" - right-justified mode, SSI is clock slave
|
|
|
- "rj-master" - r.j., SSI is clock master
|
|
|
- "ac97-slave" - AC97 mode, SSI is clock slave
|
|
|
- "ac97-master" - AC97 mode, SSI is clock master
|
|
|
-
|
|
|
- Optional properties:
|
|
|
- - codec-handle : phandle to a 'codec' node that defines an audio
|
|
|
- codec connected to this SSI. This node is typically
|
|
|
- a child of an I2C or other control node.
|
|
|
-
|
|
|
- Child 'codec' node required properties:
|
|
|
- - compatible : compatible list, contains the name of the codec
|
|
|
-
|
|
|
- Child 'codec' node optional properties:
|
|
|
- - clock-frequency : The frequency of the input clock, which typically
|
|
|
- comes from an on-board dedicated oscillator.
|
|
|
-
|
|
|
- * Freescale 83xx DMA Controller
|
|
|
-
|
|
|
- Freescale PowerPC 83xx have on chip general purpose DMA controllers.
|
|
|
-
|
|
|
- Required properties:
|
|
|
-
|
|
|
- - compatible : compatible list, contains 2 entries, first is
|
|
|
- "fsl,CHIP-dma", where CHIP is the processor
|
|
|
- (mpc8349, mpc8360, etc.) and the second is
|
|
|
- "fsl,elo-dma"
|
|
|
- - reg : <registers mapping for DMA general status reg>
|
|
|
- - ranges : Should be defined as specified in 1) to describe the
|
|
|
- DMA controller channels.
|
|
|
- - cell-index : controller index. 0 for controller @ 0x8100
|
|
|
- - interrupts : <interrupt mapping for DMA IRQ>
|
|
|
- - interrupt-parent : optional, if needed for interrupt mapping
|
|
|
-
|
|
|
-
|
|
|
- - DMA channel nodes:
|
|
|
- - compatible : compatible list, contains 2 entries, first is
|
|
|
- "fsl,CHIP-dma-channel", where CHIP is the processor
|
|
|
- (mpc8349, mpc8350, etc.) and the second is
|
|
|
- "fsl,elo-dma-channel"
|
|
|
- - reg : <registers mapping for channel>
|
|
|
- - cell-index : dma channel index starts at 0.
|
|
|
-
|
|
|
- Optional properties:
|
|
|
- - interrupts : <interrupt mapping for DMA channel IRQ>
|
|
|
- (on 83xx this is expected to be identical to
|
|
|
- the interrupts property of the parent node)
|
|
|
- - interrupt-parent : optional, if needed for interrupt mapping
|
|
|
-
|
|
|
- Example:
|
|
|
- dma@82a8 {
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <1>;
|
|
|
- compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
|
|
|
- reg = <82a8 4>;
|
|
|
- ranges = <0 8100 1a4>;
|
|
|
- interrupt-parent = <&ipic>;
|
|
|
- interrupts = <47 8>;
|
|
|
- cell-index = <0>;
|
|
|
- dma-channel@0 {
|
|
|
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
|
|
- cell-index = <0>;
|
|
|
- reg = <0 80>;
|
|
|
- };
|
|
|
- dma-channel@80 {
|
|
|
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
|
|
- cell-index = <1>;
|
|
|
- reg = <80 80>;
|
|
|
- };
|
|
|
- dma-channel@100 {
|
|
|
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
|
|
- cell-index = <2>;
|
|
|
- reg = <100 80>;
|
|
|
- };
|
|
|
- dma-channel@180 {
|
|
|
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
|
|
- cell-index = <3>;
|
|
|
- reg = <180 80>;
|
|
|
- };
|
|
|
- };
|
|
|
-
|
|
|
- * Freescale 85xx/86xx DMA Controller
|
|
|
-
|
|
|
- Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.
|
|
|
-
|
|
|
- Required properties:
|
|
|
-
|
|
|
- - compatible : compatible list, contains 2 entries, first is
|
|
|
- "fsl,CHIP-dma", where CHIP is the processor
|
|
|
- (mpc8540, mpc8540, etc.) and the second is
|
|
|
- "fsl,eloplus-dma"
|
|
|
- - reg : <registers mapping for DMA general status reg>
|
|
|
- - cell-index : controller index. 0 for controller @ 0x21000,
|
|
|
- 1 for controller @ 0xc000
|
|
|
- - ranges : Should be defined as specified in 1) to describe the
|
|
|
- DMA controller channels.
|
|
|
-
|
|
|
- - DMA channel nodes:
|
|
|
- - compatible : compatible list, contains 2 entries, first is
|
|
|
- "fsl,CHIP-dma-channel", where CHIP is the processor
|
|
|
- (mpc8540, mpc8560, etc.) and the second is
|
|
|
- "fsl,eloplus-dma-channel"
|
|
|
- - cell-index : dma channel index starts at 0.
|
|
|
- - reg : <registers mapping for channel>
|
|
|
- - interrupts : <interrupt mapping for DMA channel IRQ>
|
|
|
- - interrupt-parent : optional, if needed for interrupt mapping
|
|
|
-
|
|
|
- Example:
|
|
|
- dma@21300 {
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <1>;
|
|
|
- compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
|
|
|
- reg = <21300 4>;
|
|
|
- ranges = <0 21100 200>;
|
|
|
- cell-index = <0>;
|
|
|
- dma-channel@0 {
|
|
|
- compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
|
|
- reg = <0 80>;
|
|
|
- cell-index = <0>;
|
|
|
- interrupt-parent = <&mpic>;
|
|
|
- interrupts = <14 2>;
|
|
|
- };
|
|
|
- dma-channel@80 {
|
|
|
- compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
|
|
- reg = <80 80>;
|
|
|
- cell-index = <1>;
|
|
|
- interrupt-parent = <&mpic>;
|
|
|
- interrupts = <15 2>;
|
|
|
- };
|
|
|
- dma-channel@100 {
|
|
|
- compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
|
|
- reg = <100 80>;
|
|
|
- cell-index = <2>;
|
|
|
- interrupt-parent = <&mpic>;
|
|
|
- interrupts = <16 2>;
|
|
|
- };
|
|
|
- dma-channel@180 {
|
|
|
- compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
|
|
- reg = <180 80>;
|
|
|
- cell-index = <3>;
|
|
|
- interrupt-parent = <&mpic>;
|
|
|
- interrupts = <17 2>;
|
|
|
- };
|
|
|
- };
|
|
|
-
|
|
|
- * Freescale 8xxx/3.0 Gb/s SATA nodes
|
|
|
-
|
|
|
- SATA nodes are defined to describe on-chip Serial ATA controllers.
|
|
|
- Each SATA port should have its own node.
|
|
|
-
|
|
|
- Required properties:
|
|
|
- - compatible : compatible list, contains 2 entries, first is
|
|
|
- "fsl,CHIP-sata", where CHIP is the processor
|
|
|
- (mpc8315, mpc8379, etc.) and the second is
|
|
|
- "fsl,pq-sata"
|
|
|
- - interrupts : <interrupt mapping for SATA IRQ>
|
|
|
- - cell-index : controller index.
|
|
|
- 1 for controller @ 0x18000
|
|
|
- 2 for controller @ 0x19000
|
|
|
- 3 for controller @ 0x1a000
|
|
|
- 4 for controller @ 0x1b000
|
|
|
-
|
|
|
- Optional properties:
|
|
|
- - interrupt-parent : optional, if needed for interrupt mapping
|
|
|
- - reg : <registers mapping>
|
|
|
-
|
|
|
- Example:
|
|
|
-
|
|
|
- sata@18000 {
|
|
|
- compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
|
|
|
- reg = <0x18000 0x1000>;
|
|
|
- cell-index = <1>;
|
|
|
- interrupts = <2c 8>;
|
|
|
- interrupt-parent = < &ipic >;
|
|
|
- };
|
|
|
-
|
|
|
- q) USB EHCI controllers
|
|
|
+ f) USB EHCI controllers
|
|
|
|
|
|
Required properties:
|
|
|
- compatible : should be "usb-ehci".
|
|
@@ -2870,6 +1863,26 @@ platforms are moved over to use the flattened-device-tree model.
|
|
|
reg = <0xe8000000 32>;
|
|
|
};
|
|
|
|
|
|
+ r) MDIO on GPIOs
|
|
|
+
|
|
|
+ Currently defined compatibles:
|
|
|
+ - virtual,gpio-mdio
|
|
|
+
|
|
|
+ MDC and MDIO lines connected to GPIO controllers are listed in the
|
|
|
+ gpios property as described in section VIII.1 in the following order:
|
|
|
+
|
|
|
+ MDC, MDIO.
|
|
|
+
|
|
|
+ Example:
|
|
|
+
|
|
|
+ mdio {
|
|
|
+ compatible = "virtual,mdio-gpio";
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ gpios = <&qe_pio_a 11
|
|
|
+ &qe_pio_c 6>;
|
|
|
+ };
|
|
|
+
|
|
|
VII - Marvell Discovery mv64[345]6x System Controller chips
|
|
|
===========================================================
|
|
|
|
|
@@ -3477,8 +2490,8 @@ encodings listed below:
|
|
|
2 = high to low edge sensitive type enabled
|
|
|
3 = low to high edge sensitive type enabled
|
|
|
|
|
|
-VIII - Specifying GPIO information for devices
|
|
|
-==============================================
|
|
|
+IX - Specifying GPIO information for devices
|
|
|
+============================================
|
|
|
|
|
|
1) gpios property
|
|
|
-----------------
|
|
@@ -3526,119 +2539,151 @@ Example of two SOC GPIO banks defined as gpio-controller nodes:
|
|
|
gpio-controller;
|
|
|
};
|
|
|
|
|
|
+X - Specifying Device Power Management Information (sleep property)
|
|
|
+===================================================================
|
|
|
+
|
|
|
+Devices on SOCs often have mechanisms for placing devices into low-power
|
|
|
+states that are decoupled from the devices' own register blocks. Sometimes,
|
|
|
+this information is more complicated than a cell-index property can
|
|
|
+reasonably describe. Thus, each device controlled in such a manner
|
|
|
+may contain a "sleep" property which describes these connections.
|
|
|
+
|
|
|
+The sleep property consists of one or more sleep resources, each of
|
|
|
+which consists of a phandle to a sleep controller, followed by a
|
|
|
+controller-specific sleep specifier of zero or more cells.
|
|
|
+
|
|
|
+The semantics of what type of low power modes are possible are defined
|
|
|
+by the sleep controller. Some examples of the types of low power modes
|
|
|
+that may be supported are:
|
|
|
+
|
|
|
+ - Dynamic: The device may be disabled or enabled at any time.
|
|
|
+ - System Suspend: The device may request to be disabled or remain
|
|
|
+ awake during system suspend, but will not be disabled until then.
|
|
|
+ - Permanent: The device is disabled permanently (until the next hard
|
|
|
+ reset).
|
|
|
+
|
|
|
+Some devices may share a clock domain with each other, such that they should
|
|
|
+only be suspended when none of the devices are in use. Where reasonable,
|
|
|
+such nodes should be placed on a virtual bus, where the bus has the sleep
|
|
|
+property. If the clock domain is shared among devices that cannot be
|
|
|
+reasonably grouped in this manner, then create a virtual sleep controller
|
|
|
+(similar to an interrupt nexus, except that defining a standardized
|
|
|
+sleep-map should wait until its necessity is demonstrated).
|
|
|
+
|
|
|
Appendix A - Sample SOC node for MPC8540
|
|
|
========================================
|
|
|
|
|
|
-Note that the #address-cells and #size-cells for the SoC node
|
|
|
-in this example have been explicitly listed; these are likely
|
|
|
-not necessary as they are usually the same as the root node.
|
|
|
-
|
|
|
- soc8540@e0000000 {
|
|
|
+ soc@e0000000 {
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <1>;
|
|
|
- #interrupt-cells = <2>;
|
|
|
+ compatible = "fsl,mpc8540-ccsr", "simple-bus";
|
|
|
device_type = "soc";
|
|
|
- ranges = <00000000 e0000000 00100000>
|
|
|
- reg = <e0000000 00003000>;
|
|
|
+ ranges = <0x00000000 0xe0000000 0x00100000>
|
|
|
bus-frequency = <0>;
|
|
|
-
|
|
|
- mdio@24520 {
|
|
|
- reg = <24520 20>;
|
|
|
- device_type = "mdio";
|
|
|
- compatible = "gianfar";
|
|
|
-
|
|
|
- ethernet-phy@0 {
|
|
|
- linux,phandle = <2452000>
|
|
|
- interrupt-parent = <40000>;
|
|
|
- interrupts = <35 1>;
|
|
|
- reg = <0>;
|
|
|
- device_type = "ethernet-phy";
|
|
|
- };
|
|
|
-
|
|
|
- ethernet-phy@1 {
|
|
|
- linux,phandle = <2452001>
|
|
|
- interrupt-parent = <40000>;
|
|
|
- interrupts = <35 1>;
|
|
|
- reg = <1>;
|
|
|
- device_type = "ethernet-phy";
|
|
|
- };
|
|
|
-
|
|
|
- ethernet-phy@3 {
|
|
|
- linux,phandle = <2452002>
|
|
|
- interrupt-parent = <40000>;
|
|
|
- interrupts = <35 1>;
|
|
|
- reg = <3>;
|
|
|
- device_type = "ethernet-phy";
|
|
|
- };
|
|
|
-
|
|
|
- };
|
|
|
+ interrupt-parent = <&pic>;
|
|
|
|
|
|
ethernet@24000 {
|
|
|
- #size-cells = <0>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <1>;
|
|
|
device_type = "network";
|
|
|
model = "TSEC";
|
|
|
- compatible = "gianfar";
|
|
|
- reg = <24000 1000>;
|
|
|
- mac-address = [ 00 E0 0C 00 73 00 ];
|
|
|
- interrupts = <d 3 e 3 12 3>;
|
|
|
- interrupt-parent = <40000>;
|
|
|
- phy-handle = <2452000>;
|
|
|
+ compatible = "gianfar", "simple-bus";
|
|
|
+ reg = <0x24000 0x1000>;
|
|
|
+ local-mac-address = [ 00 E0 0C 00 73 00 ];
|
|
|
+ interrupts = <29 2 30 2 34 2>;
|
|
|
+ phy-handle = <&phy0>;
|
|
|
+ sleep = <&pmc 00000080>;
|
|
|
+ ranges;
|
|
|
+
|
|
|
+ mdio@24520 {
|
|
|
+ reg = <0x24520 0x20>;
|
|
|
+ compatible = "fsl,gianfar-mdio";
|
|
|
+
|
|
|
+ phy0: ethernet-phy@0 {
|
|
|
+ interrupts = <5 1>;
|
|
|
+ reg = <0>;
|
|
|
+ device_type = "ethernet-phy";
|
|
|
+ };
|
|
|
+
|
|
|
+ phy1: ethernet-phy@1 {
|
|
|
+ interrupts = <5 1>;
|
|
|
+ reg = <1>;
|
|
|
+ device_type = "ethernet-phy";
|
|
|
+ };
|
|
|
+
|
|
|
+ phy3: ethernet-phy@3 {
|
|
|
+ interrupts = <7 1>;
|
|
|
+ reg = <3>;
|
|
|
+ device_type = "ethernet-phy";
|
|
|
+ };
|
|
|
+ };
|
|
|
};
|
|
|
|
|
|
ethernet@25000 {
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <0>;
|
|
|
device_type = "network";
|
|
|
model = "TSEC";
|
|
|
compatible = "gianfar";
|
|
|
- reg = <25000 1000>;
|
|
|
- mac-address = [ 00 E0 0C 00 73 01 ];
|
|
|
- interrupts = <13 3 14 3 18 3>;
|
|
|
- interrupt-parent = <40000>;
|
|
|
- phy-handle = <2452001>;
|
|
|
+ reg = <0x25000 0x1000>;
|
|
|
+ local-mac-address = [ 00 E0 0C 00 73 01 ];
|
|
|
+ interrupts = <13 2 14 2 18 2>;
|
|
|
+ phy-handle = <&phy1>;
|
|
|
+ sleep = <&pmc 00000040>;
|
|
|
};
|
|
|
|
|
|
ethernet@26000 {
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <0>;
|
|
|
device_type = "network";
|
|
|
model = "FEC";
|
|
|
compatible = "gianfar";
|
|
|
- reg = <26000 1000>;
|
|
|
- mac-address = [ 00 E0 0C 00 73 02 ];
|
|
|
- interrupts = <19 3>;
|
|
|
- interrupt-parent = <40000>;
|
|
|
- phy-handle = <2452002>;
|
|
|
+ reg = <0x26000 0x1000>;
|
|
|
+ local-mac-address = [ 00 E0 0C 00 73 02 ];
|
|
|
+ interrupts = <41 2>;
|
|
|
+ phy-handle = <&phy3>;
|
|
|
+ sleep = <&pmc 00000020>;
|
|
|
};
|
|
|
|
|
|
serial@4500 {
|
|
|
- device_type = "serial";
|
|
|
- compatible = "ns16550";
|
|
|
- reg = <4500 100>;
|
|
|
- clock-frequency = <0>;
|
|
|
- interrupts = <1a 3>;
|
|
|
- interrupt-parent = <40000>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <1>;
|
|
|
+ compatible = "fsl,mpc8540-duart", "simple-bus";
|
|
|
+ sleep = <&pmc 00000002>;
|
|
|
+ ranges;
|
|
|
+
|
|
|
+ serial@4500 {
|
|
|
+ device_type = "serial";
|
|
|
+ compatible = "ns16550";
|
|
|
+ reg = <0x4500 0x100>;
|
|
|
+ clock-frequency = <0>;
|
|
|
+ interrupts = <42 2>;
|
|
|
+ };
|
|
|
+
|
|
|
+ serial@4600 {
|
|
|
+ device_type = "serial";
|
|
|
+ compatible = "ns16550";
|
|
|
+ reg = <0x4600 0x100>;
|
|
|
+ clock-frequency = <0>;
|
|
|
+ interrupts = <42 2>;
|
|
|
+ };
|
|
|
};
|
|
|
|
|
|
- pic@40000 {
|
|
|
- linux,phandle = <40000>;
|
|
|
- clock-frequency = <0>;
|
|
|
+ pic: pic@40000 {
|
|
|
interrupt-controller;
|
|
|
#address-cells = <0>;
|
|
|
- reg = <40000 40000>;
|
|
|
- built-in;
|
|
|
+ #interrupt-cells = <2>;
|
|
|
+ reg = <0x40000 0x40000>;
|
|
|
compatible = "chrp,open-pic";
|
|
|
device_type = "open-pic";
|
|
|
- big-endian;
|
|
|
};
|
|
|
|
|
|
i2c@3000 {
|
|
|
- interrupt-parent = <40000>;
|
|
|
- interrupts = <1b 3>;
|
|
|
- reg = <3000 18>;
|
|
|
- device_type = "i2c";
|
|
|
+ interrupts = <43 2>;
|
|
|
+ reg = <0x3000 0x100>;
|
|
|
compatible = "fsl-i2c";
|
|
|
dfsrr;
|
|
|
+ sleep = <&pmc 00000004>;
|
|
|
};
|
|
|
|
|
|
+ pmc: power@e0070 {
|
|
|
+ compatible = "fsl,mpc8540-pmc", "fsl,mpc8548-pmc";
|
|
|
+ reg = <0xe0070 0x20>;
|
|
|
+ };
|
|
|
};
|