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@@ -83,17 +83,6 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
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writel(value, pcie->base + offset);
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}
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-static inline u32 dra7xx_pcie_readl_rc(struct pcie_port *pp, u32 offset)
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-{
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- return readl(pp->dbi_base + offset);
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-}
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-
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-static inline void dra7xx_pcie_writel_rc(struct pcie_port *pp, u32 offset,
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- u32 value)
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-{
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- writel(value, pp->dbi_base + offset);
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-}
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-
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static int dra7xx_pcie_link_up(struct pcie_port *pp)
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{
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
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@@ -448,9 +437,9 @@ static int dra7xx_pcie_suspend(struct device *dev)
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u32 val;
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/* clear MSE */
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- val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);
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+ val = dw_pcie_readl_rc(pp, PCI_COMMAND);
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val &= ~PCI_COMMAND_MEMORY;
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- dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);
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+ dw_pcie_writel_rc(pp, PCI_COMMAND, val);
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return 0;
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}
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@@ -462,9 +451,9 @@ static int dra7xx_pcie_resume(struct device *dev)
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u32 val;
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/* set MSE */
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- val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);
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+ val = dw_pcie_readl_rc(pp, PCI_COMMAND);
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val |= PCI_COMMAND_MEMORY;
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- dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);
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+ dw_pcie_writel_rc(pp, PCI_COMMAND, val);
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return 0;
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}
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