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@@ -1038,11 +1038,12 @@ void do_machine_check(struct pt_regs *regs, long error_code)
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int i;
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int worst = 0;
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int severity;
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+
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/*
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* Establish sequential order between the CPUs entering the machine
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* check handler.
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*/
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- int order;
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+ int order = -1;
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/*
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* If no_way_out gets set, there is no safe way to recover from this
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* MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
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@@ -1056,7 +1057,12 @@ void do_machine_check(struct pt_regs *regs, long error_code)
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DECLARE_BITMAP(toclear, MAX_NR_BANKS);
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DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
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char *msg = "Unknown";
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- int lmce = 0;
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+
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+ /*
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+ * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
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+ * on Intel.
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+ */
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+ int lmce = 1;
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/* If this CPU is offline, just bail out. */
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if (cpu_is_offline(smp_processor_id())) {
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@@ -1095,19 +1101,20 @@ void do_machine_check(struct pt_regs *regs, long error_code)
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kill_it = 1;
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/*
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- * Check if this MCE is signaled to only this logical processor
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+ * Check if this MCE is signaled to only this logical processor,
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+ * on Intel only.
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*/
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- if (m.mcgstatus & MCG_STATUS_LMCES)
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- lmce = 1;
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- else {
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- /*
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- * Go through all the banks in exclusion of the other CPUs.
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- * This way we don't report duplicated events on shared banks
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- * because the first one to see it will clear it.
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- * If this is a Local MCE, then no need to perform rendezvous.
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- */
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+ if (m.cpuvendor == X86_VENDOR_INTEL)
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+ lmce = m.mcgstatus & MCG_STATUS_LMCES;
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+
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+ /*
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+ * Go through all banks in exclusion of the other CPUs. This way we
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+ * don't report duplicated events on shared banks because the first one
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+ * to see it will clear it. If this is a Local MCE, then no need to
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+ * perform rendezvous.
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+ */
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+ if (!lmce)
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order = mce_start(&no_way_out);
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- }
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for (i = 0; i < cfg->banks; i++) {
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__clear_bit(i, toclear);
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