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@@ -973,6 +973,39 @@ static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
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return max_bitflips;
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}
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+static int sunxi_nfc_hw_ecc_read_subpage(struct mtd_info *mtd,
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+ struct nand_chip *chip,
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+ u32 data_offs, u32 readlen,
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+ u8 *bufpoi, int page)
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+{
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+ struct nand_ecc_ctrl *ecc = &chip->ecc;
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+ int ret, i, cur_off = 0;
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+ unsigned int max_bitflips = 0;
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+
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+ sunxi_nfc_hw_ecc_enable(mtd);
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+
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+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
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+ for (i = data_offs / ecc->size;
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+ i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) {
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+ int data_off = i * ecc->size;
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+ int oob_off = i * (ecc->bytes + 4);
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+ u8 *data = bufpoi + data_off;
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+ u8 *oob = chip->oob_poi + oob_off;
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+
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+ ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off,
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+ oob,
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+ oob_off + mtd->writesize,
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+ &cur_off, &max_bitflips,
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+ !i, page);
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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+ sunxi_nfc_hw_ecc_disable(mtd);
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+
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+ return max_bitflips;
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+}
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+
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static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
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struct nand_chip *chip,
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const uint8_t *buf, int oob_required,
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@@ -1389,6 +1422,7 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
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ecc->write_page = sunxi_nfc_hw_ecc_write_page;
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ecc->read_oob_raw = nand_read_oob_std;
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ecc->write_oob_raw = nand_write_oob_std;
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+ ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage;
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layout = ecc->layout;
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nsectors = mtd->writesize / ecc->size;
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@@ -1635,6 +1669,8 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
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if (nand->options & NAND_NEED_SCRAMBLING)
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nand->options |= NAND_NO_SUBPAGE_WRITE;
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+ nand->options |= NAND_SUBPAGE_READ;
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+
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ret = sunxi_nand_chip_init_timings(chip, np);
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if (ret) {
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dev_err(dev, "could not configure chip timings: %d\n", ret);
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