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@@ -256,6 +256,18 @@ noinline void local_flush_tlb_all(void)
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
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}
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+ if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE)) {
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+ const int stlb_idx = 0x800;
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+
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+ /* Blank sTLB entry */
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+ write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ);
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+
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+ for (entry = stlb_idx; entry < stlb_idx + 16; entry++) {
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+ write_aux_reg(ARC_REG_TLBINDEX, entry);
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+ write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
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+ }
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+ }
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+
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utlb_invalidate();
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local_irq_restore(flags);
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@@ -580,6 +592,75 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
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}
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}
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+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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+
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+/*
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+ * MMUv4 in HS38x cores supports Super Pages which are basis for Linux THP
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+ * support.
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+ *
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+ * Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a
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+ * new bit "SZ" in TLB page desciptor to distinguish between them.
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+ * Super Page size is configurable in hardware (4K to 16M), but fixed once
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+ * RTL builds.
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+ *
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+ * The exact THP size a Linx configuration will support is a function of:
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+ * - MMU page size (typical 8K, RTL fixed)
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+ * - software page walker address split between PGD:PTE:PFN (typical
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+ * 11:8:13, but can be changed with 1 line)
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+ * So for above default, THP size supported is 8K * (2^8) = 2M
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+ *
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+ * Default Page Walker is 2 levels, PGD:PTE:PFN, which in THP regime
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+ * reduces to 1 level (as PTE is folded into PGD and canonically referred
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+ * to as PMD).
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+ * Thus THP PMD accessors are implemented in terms of PTE (just like sparc)
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+ */
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+
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+void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
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+ pmd_t *pmd)
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+{
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+ pte_t pte = __pte(pmd_val(*pmd));
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+ update_mmu_cache(vma, addr, &pte);
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+}
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+
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+void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
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+ pgtable_t pgtable)
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+{
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+ struct list_head *lh = (struct list_head *) pgtable;
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+
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+ assert_spin_locked(&mm->page_table_lock);
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+
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+ /* FIFO */
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+ if (!pmd_huge_pte(mm, pmdp))
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+ INIT_LIST_HEAD(lh);
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+ else
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+ list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
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+ pmd_huge_pte(mm, pmdp) = pgtable;
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+}
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+
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+pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
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+{
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+ struct list_head *lh;
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+ pgtable_t pgtable;
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+
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+ assert_spin_locked(&mm->page_table_lock);
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+
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+ pgtable = pmd_huge_pte(mm, pmdp);
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+ lh = (struct list_head *) pgtable;
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+ if (list_empty(lh))
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+ pmd_huge_pte(mm, pmdp) = NULL;
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+ else {
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+ pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
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+ list_del(lh);
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+ }
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+
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+ pte_val(pgtable[0]) = 0;
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+ pte_val(pgtable[1]) = 0;
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+
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+ return pgtable;
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+}
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+
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+#endif
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+
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/* Read the Cache Build Confuration Registers, Decode them and save into
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* the cpuinfo structure for later use.
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* No Validation is done here, simply read/convert the BCRs
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Vineet Gupta