|
@@ -135,10 +135,29 @@ static char *bcm_sf2_sw_probe(struct device *host_dev, int sw_addr)
|
|
return "Broadcom Starfighter 2";
|
|
return "Broadcom Starfighter 2";
|
|
}
|
|
}
|
|
|
|
|
|
-static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
|
|
|
|
|
|
+static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
|
|
{
|
|
{
|
|
struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
unsigned int i;
|
|
unsigned int i;
|
|
|
|
+ u32 reg;
|
|
|
|
+
|
|
|
|
+ /* Enable the IMP Port to be in the same VLAN as the other ports
|
|
|
|
+ * on a per-port basis such that we only have Port i and IMP in
|
|
|
|
+ * the same VLAN.
|
|
|
|
+ */
|
|
|
|
+ for (i = 0; i < priv->hw_params.num_ports; i++) {
|
|
|
|
+ if (!((1 << i) & ds->phys_port_mask))
|
|
|
|
+ continue;
|
|
|
|
+
|
|
|
|
+ reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
|
|
|
|
+ reg |= (1 << cpu_port);
|
|
|
|
+ core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
|
|
|
|
+ }
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
|
|
|
|
+{
|
|
|
|
+ struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
u32 reg, val;
|
|
u32 reg, val;
|
|
|
|
|
|
/* Enable the port memories */
|
|
/* Enable the port memories */
|
|
@@ -199,24 +218,26 @@ static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
|
|
reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
|
|
reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
|
|
reg |= (MII_SW_OR | LINK_STS);
|
|
reg |= (MII_SW_OR | LINK_STS);
|
|
core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
|
|
core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
|
|
|
|
+}
|
|
|
|
|
|
- /* Enable the IMP Port to be in the same VLAN as the other ports
|
|
|
|
- * on a per-port basis such that we only have Port i and IMP in
|
|
|
|
- * the same VLAN.
|
|
|
|
- */
|
|
|
|
- for (i = 0; i < priv->hw_params.num_ports; i++) {
|
|
|
|
- if (!((1 << i) & ds->phys_port_mask))
|
|
|
|
- continue;
|
|
|
|
|
|
+static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
|
|
|
|
+{
|
|
|
|
+ struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
|
|
+ u32 reg;
|
|
|
|
|
|
- reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
|
|
|
|
- reg |= (1 << port);
|
|
|
|
- core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
|
|
|
|
- }
|
|
|
|
|
|
+ reg = core_readl(priv, CORE_EEE_EN_CTRL);
|
|
|
|
+ if (enable)
|
|
|
|
+ reg |= 1 << port;
|
|
|
|
+ else
|
|
|
|
+ reg &= ~(1 << port);
|
|
|
|
+ core_writel(priv, reg, CORE_EEE_EN_CTRL);
|
|
}
|
|
}
|
|
|
|
|
|
-static void bcm_sf2_port_setup(struct dsa_switch *ds, int port)
|
|
|
|
|
|
+static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
|
|
|
|
+ struct phy_device *phy)
|
|
{
|
|
{
|
|
struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
|
|
+ s8 cpu_port = ds->dst[ds->index].cpu_port;
|
|
u32 reg;
|
|
u32 reg;
|
|
|
|
|
|
/* Clear the memory power down */
|
|
/* Clear the memory power down */
|
|
@@ -236,9 +257,18 @@ static void bcm_sf2_port_setup(struct dsa_switch *ds, int port)
|
|
reg &= ~PORT_VLAN_CTRL_MASK;
|
|
reg &= ~PORT_VLAN_CTRL_MASK;
|
|
reg |= (1 << port);
|
|
reg |= (1 << port);
|
|
core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
|
|
core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
|
|
|
|
+
|
|
|
|
+ bcm_sf2_imp_vlan_setup(ds, cpu_port);
|
|
|
|
+
|
|
|
|
+ /* If EEE was enabled, restore it */
|
|
|
|
+ if (priv->port_sts[port].eee.eee_enabled)
|
|
|
|
+ bcm_sf2_eee_enable_set(ds, port, true);
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
}
|
|
}
|
|
|
|
|
|
-static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
|
|
|
|
|
|
+static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
|
|
|
|
+ struct phy_device *phy)
|
|
{
|
|
{
|
|
struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
u32 off, reg;
|
|
u32 off, reg;
|
|
@@ -246,6 +276,11 @@ static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
|
|
if (priv->wol_ports_mask & (1 << port))
|
|
if (priv->wol_ports_mask & (1 << port))
|
|
return;
|
|
return;
|
|
|
|
|
|
|
|
+ if (port == 7) {
|
|
|
|
+ intrl2_1_mask_set(priv, P_IRQ_MASK(P7_IRQ_OFF));
|
|
|
|
+ intrl2_1_writel(priv, P_IRQ_MASK(P7_IRQ_OFF), INTRL2_CPU_CLEAR);
|
|
|
|
+ }
|
|
|
|
+
|
|
if (dsa_is_cpu_port(ds, port))
|
|
if (dsa_is_cpu_port(ds, port))
|
|
off = CORE_IMP_CTL;
|
|
off = CORE_IMP_CTL;
|
|
else
|
|
else
|
|
@@ -261,6 +296,60 @@ static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
|
|
core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
|
|
core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
|
|
}
|
|
}
|
|
|
|
|
|
|
|
+/* Returns 0 if EEE was not enabled, or 1 otherwise
|
|
|
|
+ */
|
|
|
|
+static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
|
|
|
|
+ struct phy_device *phy)
|
|
|
|
+{
|
|
|
|
+ struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
|
|
+ struct ethtool_eee *p = &priv->port_sts[port].eee;
|
|
|
|
+ int ret;
|
|
|
|
+
|
|
|
|
+ p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
|
|
|
|
+
|
|
|
|
+ ret = phy_init_eee(phy, 0);
|
|
|
|
+ if (ret)
|
|
|
|
+ return 0;
|
|
|
|
+
|
|
|
|
+ bcm_sf2_eee_enable_set(ds, port, true);
|
|
|
|
+
|
|
|
|
+ return 1;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
|
|
|
|
+ struct ethtool_eee *e)
|
|
|
|
+{
|
|
|
|
+ struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
|
|
+ struct ethtool_eee *p = &priv->port_sts[port].eee;
|
|
|
|
+ u32 reg;
|
|
|
|
+
|
|
|
|
+ reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
|
|
|
|
+ e->eee_enabled = p->eee_enabled;
|
|
|
|
+ e->eee_active = !!(reg & (1 << port));
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
|
|
|
|
+ struct phy_device *phydev,
|
|
|
|
+ struct ethtool_eee *e)
|
|
|
|
+{
|
|
|
|
+ struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
|
|
|
+ struct ethtool_eee *p = &priv->port_sts[port].eee;
|
|
|
|
+
|
|
|
|
+ p->eee_enabled = e->eee_enabled;
|
|
|
|
+
|
|
|
|
+ if (!p->eee_enabled) {
|
|
|
|
+ bcm_sf2_eee_enable_set(ds, port, false);
|
|
|
|
+ } else {
|
|
|
|
+ p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
|
|
|
|
+ if (!p->eee_enabled)
|
|
|
|
+ return -EOPNOTSUPP;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
|
|
static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
|
|
{
|
|
{
|
|
struct bcm_sf2_priv *priv = dev_id;
|
|
struct bcm_sf2_priv *priv = dev_id;
|
|
@@ -363,11 +452,11 @@ static int bcm_sf2_sw_setup(struct dsa_switch *ds)
|
|
for (port = 0; port < priv->hw_params.num_ports; port++) {
|
|
for (port = 0; port < priv->hw_params.num_ports; port++) {
|
|
/* IMP port receives special treatment */
|
|
/* IMP port receives special treatment */
|
|
if ((1 << port) & ds->phys_port_mask)
|
|
if ((1 << port) & ds->phys_port_mask)
|
|
- bcm_sf2_port_setup(ds, port);
|
|
|
|
|
|
+ bcm_sf2_port_setup(ds, port, NULL);
|
|
else if (dsa_is_cpu_port(ds, port))
|
|
else if (dsa_is_cpu_port(ds, port))
|
|
bcm_sf2_imp_setup(ds, port);
|
|
bcm_sf2_imp_setup(ds, port);
|
|
else
|
|
else
|
|
- bcm_sf2_port_disable(ds, port);
|
|
|
|
|
|
+ bcm_sf2_port_disable(ds, port, NULL);
|
|
}
|
|
}
|
|
|
|
|
|
/* Include the pseudo-PHY address and the broadcast PHY address to
|
|
/* Include the pseudo-PHY address and the broadcast PHY address to
|
|
@@ -506,6 +595,15 @@ static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
|
|
port_mode = EXT_REVMII;
|
|
port_mode = EXT_REVMII;
|
|
break;
|
|
break;
|
|
default:
|
|
default:
|
|
|
|
+ /* All other PHYs: internal and MoCA */
|
|
|
|
+ goto force_link;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ /* If the link is down, just disable the interface to conserve power */
|
|
|
|
+ if (!phydev->link) {
|
|
|
|
+ reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
|
|
|
|
+ reg &= ~RGMII_MODE_EN;
|
|
|
|
+ reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
|
|
goto force_link;
|
|
goto force_link;
|
|
}
|
|
}
|
|
|
|
|
|
@@ -629,7 +727,7 @@ static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
|
|
for (port = 0; port < DSA_MAX_PORTS; port++) {
|
|
for (port = 0; port < DSA_MAX_PORTS; port++) {
|
|
if ((1 << port) & ds->phys_port_mask ||
|
|
if ((1 << port) & ds->phys_port_mask ||
|
|
dsa_is_cpu_port(ds, port))
|
|
dsa_is_cpu_port(ds, port))
|
|
- bcm_sf2_port_disable(ds, port);
|
|
|
|
|
|
+ bcm_sf2_port_disable(ds, port, NULL);
|
|
}
|
|
}
|
|
|
|
|
|
return 0;
|
|
return 0;
|
|
@@ -685,7 +783,7 @@ static int bcm_sf2_sw_resume(struct dsa_switch *ds)
|
|
|
|
|
|
for (port = 0; port < DSA_MAX_PORTS; port++) {
|
|
for (port = 0; port < DSA_MAX_PORTS; port++) {
|
|
if ((1 << port) & ds->phys_port_mask)
|
|
if ((1 << port) & ds->phys_port_mask)
|
|
- bcm_sf2_port_setup(ds, port);
|
|
|
|
|
|
+ bcm_sf2_port_setup(ds, port, NULL);
|
|
else if (dsa_is_cpu_port(ds, port))
|
|
else if (dsa_is_cpu_port(ds, port))
|
|
bcm_sf2_imp_setup(ds, port);
|
|
bcm_sf2_imp_setup(ds, port);
|
|
}
|
|
}
|
|
@@ -763,6 +861,10 @@ static struct dsa_switch_driver bcm_sf2_switch_driver = {
|
|
.resume = bcm_sf2_sw_resume,
|
|
.resume = bcm_sf2_sw_resume,
|
|
.get_wol = bcm_sf2_sw_get_wol,
|
|
.get_wol = bcm_sf2_sw_get_wol,
|
|
.set_wol = bcm_sf2_sw_set_wol,
|
|
.set_wol = bcm_sf2_sw_set_wol,
|
|
|
|
+ .port_enable = bcm_sf2_port_setup,
|
|
|
|
+ .port_disable = bcm_sf2_port_disable,
|
|
|
|
+ .get_eee = bcm_sf2_sw_get_eee,
|
|
|
|
+ .set_eee = bcm_sf2_sw_set_eee,
|
|
};
|
|
};
|
|
|
|
|
|
static int __init bcm_sf2_init(void)
|
|
static int __init bcm_sf2_init(void)
|