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@@ -47,6 +47,7 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
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struct dev_pm_opp *opp;
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unsigned long freq_hz, volt, volt_old;
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unsigned int old_freq, new_freq;
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+ bool pll1_sys_temp_enabled = false;
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int ret;
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new_freq = freq_table[index].frequency;
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@@ -124,6 +125,10 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
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if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
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clk_set_rate(pll1_sys_clk, new_freq * 1000);
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clk_set_parent(pll1_sw_clk, pll1_sys_clk);
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+ } else {
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+ /* pll1_sys needs to be enabled for divider rate change to work. */
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+ pll1_sys_temp_enabled = true;
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+ clk_prepare_enable(pll1_sys_clk);
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}
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}
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@@ -135,6 +140,10 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
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return ret;
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}
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+ /* PLL1 is only needed until after ARM-PODF is set. */
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+ if (pll1_sys_temp_enabled)
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+ clk_disable_unprepare(pll1_sys_clk);
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+
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/* scaling down? scale voltage after frequency */
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if (new_freq < old_freq) {
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ret = regulator_set_voltage_tol(arm_reg, volt, 0);
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