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@@ -67,7 +67,7 @@ void intel_guc_init_early(struct intel_guc *guc)
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guc->notify = gen8_guc_raise_irq;
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}
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-static u32 get_gttype(struct drm_i915_private *dev_priv)
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+static u32 get_gt_type(struct drm_i915_private *dev_priv)
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{
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/* XXX: GT type based on PCI device ID? field seems unused by fw */
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return 0;
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@@ -98,11 +98,11 @@ void intel_guc_init_params(struct intel_guc *guc)
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u32 params[GUC_CTL_MAX_DWORDS];
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int i;
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- memset(¶ms, 0, sizeof(params));
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+ memset(params, 0, sizeof(params));
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params[GUC_CTL_DEVICE_INFO] |=
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- (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
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- (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
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+ (get_gt_type(dev_priv) << GUC_CTL_GT_TYPE_SHIFT) |
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+ (get_core_family(dev_priv) << GUC_CTL_CORE_FAMILY_SHIFT);
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/*
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* GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
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@@ -122,8 +122,9 @@ void intel_guc_init_params(struct intel_guc *guc)
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if (i915_modparams.guc_log_level >= 0) {
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params[GUC_CTL_DEBUG] =
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i915_modparams.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
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- } else
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+ } else {
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params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
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+ }
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/* If GuC submission is enabled, set up additional parameters here */
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if (i915_modparams.enable_guc_submission) {
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