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@@ -681,7 +681,7 @@ static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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* The clock divider is based off the hrawclk, and would like to run at
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* 2MHz. So, take the hrawclk value and divide by 2 and use that
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*/
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- return index ? 0 : intel_hrawclk(dev) / 2;
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+ return index ? 0 : DIV_ROUND_CLOSEST(intel_hrawclk(dev), 2);
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}
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static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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@@ -694,10 +694,10 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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return 0;
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if (intel_dig_port->port == PORT_A) {
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- return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);
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+ return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
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} else {
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- return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
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+ return DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2);
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}
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}
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@@ -719,7 +719,7 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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default: return 0;
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}
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} else {
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- return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
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+ return index ? 0 : DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2);
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}
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}
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