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@@ -32,6 +32,7 @@
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#define DP83867_CFG3 0x1e
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/* Extended Registers */
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+#define DP83867_CFG4 0x0031
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#define DP83867_RGMIICTL 0x0032
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#define DP83867_RGMIIDCTL 0x0086
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#define DP83867_IO_MUX_CFG 0x0170
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@@ -70,11 +71,21 @@
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#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
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#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
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+/* CFG4 bits */
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+#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
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+
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+enum {
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+ DP83867_PORT_MIRROING_KEEP,
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+ DP83867_PORT_MIRROING_EN,
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+ DP83867_PORT_MIRROING_DIS,
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+};
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+
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struct dp83867_private {
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int rx_id_delay;
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int tx_id_delay;
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int fifo_depth;
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int io_impedance;
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+ int port_mirroring;
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};
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static int dp83867_ack_interrupt(struct phy_device *phydev)
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@@ -111,6 +122,24 @@ static int dp83867_config_intr(struct phy_device *phydev)
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return phy_write(phydev, MII_DP83867_MICR, micr_status);
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}
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+static int dp83867_config_port_mirroring(struct phy_device *phydev)
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+{
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+ struct dp83867_private *dp83867 =
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+ (struct dp83867_private *)phydev->priv;
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+ u16 val;
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+
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+ val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR);
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+
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+ if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
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+ val |= DP83867_CFG4_PORT_MIRROR_EN;
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+ else
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+ val &= ~DP83867_CFG4_PORT_MIRROR_EN;
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+
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+ phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR, val);
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+
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+ return 0;
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+}
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+
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#ifdef CONFIG_OF_MDIO
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static int dp83867_of_init(struct phy_device *phydev)
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{
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@@ -144,6 +173,12 @@ static int dp83867_of_init(struct phy_device *phydev)
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
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return ret;
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+ if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
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+ dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
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+
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+ if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
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+ dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
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+
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return of_property_read_u32(of_node, "ti,fifo-depth",
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&dp83867->fifo_depth);
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}
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@@ -228,6 +263,9 @@ static int dp83867_config_init(struct phy_device *phydev)
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phy_write(phydev, DP83867_CFG3, val);
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}
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+ if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
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+ dp83867_config_port_mirroring(phydev);
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+
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return 0;
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}
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