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@@ -46,7 +46,11 @@
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#define AZX_DCAPS_REVERSE_ASSIGN (1 << 24) /* Assign devices in reverse order */
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#define AZX_DCAPS_REVERSE_ASSIGN (1 << 24) /* Assign devices in reverse order */
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#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
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#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
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#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
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#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
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+#ifdef CONFIG_SND_HDA_I915
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#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */
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#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */
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+#else
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+#define AZX_DCAPS_I915_POWERWELL 0 /* NOP */
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+#endif
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#define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */
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#define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */
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#define AZX_DCAPS_NO_MSI64 (1 << 29) /* Stick to 32-bit MSIs */
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#define AZX_DCAPS_NO_MSI64 (1 << 29) /* Stick to 32-bit MSIs */
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#define AZX_DCAPS_SEPARATE_STREAM_TAG (1 << 30) /* capture and playback use separate stream tag */
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#define AZX_DCAPS_SEPARATE_STREAM_TAG (1 << 30) /* capture and playback use separate stream tag */
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