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@@ -1085,23 +1085,14 @@ static u16 sdhci_get_preset_value(struct sdhci_host *host)
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return preset;
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return preset;
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}
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}
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-void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
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+u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
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+ unsigned int *actual_clock)
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{
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{
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int div = 0; /* Initialized for compiler warning */
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int div = 0; /* Initialized for compiler warning */
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int real_div = div, clk_mul = 1;
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int real_div = div, clk_mul = 1;
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u16 clk = 0;
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u16 clk = 0;
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- unsigned long timeout;
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bool switch_base_clk = false;
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bool switch_base_clk = false;
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- host->mmc->actual_clock = 0;
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-
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- sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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- if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
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- mdelay(1);
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-
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- if (clock == 0)
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- return;
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-
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if (host->version >= SDHCI_SPEC_300) {
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if (host->version >= SDHCI_SPEC_300) {
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if (host->preset_enabled) {
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if (host->preset_enabled) {
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u16 pre_val;
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u16 pre_val;
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@@ -1178,10 +1169,31 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
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clock_set:
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clock_set:
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if (real_div)
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if (real_div)
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- host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
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+ *actual_clock = (host->max_clk * clk_mul) / real_div;
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clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
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clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
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clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
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clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
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<< SDHCI_DIVIDER_HI_SHIFT;
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<< SDHCI_DIVIDER_HI_SHIFT;
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+
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+ return clk;
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+}
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+EXPORT_SYMBOL_GPL(sdhci_calc_clk);
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+
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+void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
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+{
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+ u16 clk;
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+ unsigned long timeout;
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+
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+ host->mmc->actual_clock = 0;
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+
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+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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+ if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
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+ mdelay(1);
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+
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+ if (clock == 0)
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+ return;
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+
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+ clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
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+
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clk |= SDHCI_CLOCK_INT_EN;
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clk |= SDHCI_CLOCK_INT_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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