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@@ -5436,7 +5436,7 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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}
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-static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
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+static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
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{
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int min_freq = 15;
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unsigned int gpu_freq;
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@@ -5520,16 +5520,6 @@ static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
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}
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}
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-void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
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-{
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- if (!HAS_CORE_RING_FREQ(dev_priv))
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- return;
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-
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- mutex_lock(&dev_priv->rps.hw_lock);
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- __gen6_update_ring_freq(dev_priv);
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- mutex_unlock(&dev_priv->rps.hw_lock);
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-}
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-
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static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
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{
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u32 val, rp0;
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@@ -6624,13 +6614,13 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
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gen9_enable_rc6(dev_priv);
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gen9_enable_rps(dev_priv);
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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- __gen6_update_ring_freq(dev_priv);
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+ gen6_update_ring_freq(dev_priv);
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} else if (IS_BROADWELL(dev_priv)) {
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gen8_enable_rps(dev_priv);
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- __gen6_update_ring_freq(dev_priv);
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+ gen6_update_ring_freq(dev_priv);
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} else if (INTEL_GEN(dev_priv) >= 6) {
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gen6_enable_rps(dev_priv);
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- __gen6_update_ring_freq(dev_priv);
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+ gen6_update_ring_freq(dev_priv);
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} else if (IS_IRONLAKE_M(dev_priv)) {
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ironlake_enable_drps(dev_priv);
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intel_init_emon(dev_priv);
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