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@@ -571,3 +571,40 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F5,
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quirk_amd_nb_node);
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#endif
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+
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+#ifdef CONFIG_PCI
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+/*
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+ * Processor does not ensure DRAM scrub read/write sequence
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+ * is atomic wrt accesses to CC6 save state area. Therefore
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+ * if a concurrent scrub read/write access is to same address
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+ * the entry may appear as if it is not written. This quirk
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+ * applies to Fam16h models 00h-0Fh
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+ *
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+ * See "Revision Guide" for AMD F16h models 00h-0fh,
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+ * document 51810 rev. 3.04, Nov 2013
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+ */
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+static void amd_disable_seq_and_redirect_scrub(struct pci_dev *dev)
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+{
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+ u32 val;
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+
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+ /*
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+ * Suggested workaround:
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+ * set D18F3x58[4:0] = 00h and set D18F3x5C[0] = 0b
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+ */
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+ pci_read_config_dword(dev, 0x58, &val);
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+ if (val & 0x1F) {
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+ val &= ~(0x1F);
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+ pci_write_config_dword(dev, 0x58, val);
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+ }
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+
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+ pci_read_config_dword(dev, 0x5C, &val);
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+ if (val & BIT(0)) {
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+ val &= ~BIT(0);
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+ pci_write_config_dword(dev, 0x5c, val);
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+ }
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+}
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+
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3,
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+ amd_disable_seq_and_redirect_scrub);
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+
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+#endif
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