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+/*
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+ * Copyright 2018 Advanced Micro Devices, Inc.
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a
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+ * copy of this software and associated documentation files (the "Software"),
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+ * to deal in the Software without restriction, including without limitation
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+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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+ * and/or sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be included in
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+ * all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ *
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+ *
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+ */
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+#include <linux/list.h>
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+#include "amdgpu.h"
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+#include "amdgpu_psp.h"
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+
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+
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+static DEFINE_MUTEX(xgmi_mutex);
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+
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+#define AMDGPU_MAX_XGMI_HIVE 8
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+#define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE 4
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+
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+struct amdgpu_hive_info {
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+ uint64_t hive_id;
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+ struct list_head device_list;
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+};
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+
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+static struct amdgpu_hive_info xgmi_hives[AMDGPU_MAX_XGMI_HIVE];
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+static unsigned hive_count = 0;
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+
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+static struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
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+{
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+ int i;
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+ struct amdgpu_hive_info *tmp;
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+
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+ if (!adev->gmc.xgmi.hive_id)
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+ return NULL;
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+ for (i = 0 ; i < hive_count; ++i) {
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+ tmp = &xgmi_hives[i];
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+ if (tmp->hive_id == adev->gmc.xgmi.hive_id)
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+ return tmp;
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+ }
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+ if (i >= AMDGPU_MAX_XGMI_HIVE)
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+ return NULL;
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+
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+ /* initialize new hive if not exist */
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+ tmp = &xgmi_hives[hive_count++];
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+ tmp->hive_id = adev->gmc.xgmi.hive_id;
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+ INIT_LIST_HEAD(&tmp->device_list);
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+ return tmp;
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+}
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+
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+int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
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+{
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+ struct psp_xgmi_topology_info tmp_topology[AMDGPU_MAX_XGMI_DEVICE_PER_HIVE];
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+ struct amdgpu_hive_info *hive;
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+ struct amdgpu_xgmi *entry;
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+ struct amdgpu_device *tmp_adev;
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+
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+ int count = 0, ret = -EINVAL;
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+
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+ if ((adev->asic_type < CHIP_VEGA20) ||
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+ (adev->flags & AMD_IS_APU) )
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+ return 0;
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+ adev->gmc.xgmi.device_id = psp_xgmi_get_device_id(&adev->psp);
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+ adev->gmc.xgmi.hive_id = psp_xgmi_get_hive_id(&adev->psp);
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+
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+ memset(&tmp_topology[0], 0, sizeof(tmp_topology));
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+ mutex_lock(&xgmi_mutex);
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+ hive = amdgpu_get_xgmi_hive(adev);
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+ if (!hive)
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+ goto exit;
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+
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+ list_add_tail(&adev->gmc.xgmi.head, &hive->device_list);
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+ list_for_each_entry(entry, &hive->device_list, head)
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+ tmp_topology[count++].device_id = entry->device_id;
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+
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+ ret = psp_xgmi_get_topology_info(&adev->psp, count, tmp_topology);
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+ if (ret) {
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+ dev_err(adev->dev,
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+ "XGMI: Get topology failure on device %llx, hive %llx, ret %d",
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+ adev->gmc.xgmi.device_id,
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+ adev->gmc.xgmi.hive_id, ret);
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+ goto exit;
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+ }
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+ /* Each psp need to set the latest topology */
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+ list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
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+ ret = psp_xgmi_set_topology_info(&tmp_adev->psp, count, tmp_topology);
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+ if (ret) {
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+ dev_err(tmp_adev->dev,
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+ "XGMI: Set topology failure on device %llx, hive %llx, ret %d",
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+ tmp_adev->gmc.xgmi.device_id,
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+ tmp_adev->gmc.xgmi.hive_id, ret);
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+ /* To do : continue with some node failed or disable the whole hive */
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+ break;
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+ }
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+ }
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+ if (!ret)
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+ dev_info(adev->dev, "XGMI: Add node %d to hive 0x%llx.\n",
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+ adev->gmc.xgmi.physical_node_id,
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+ adev->gmc.xgmi.hive_id);
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+
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+exit:
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+ mutex_unlock(&xgmi_mutex);
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+ return ret;
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+}
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+
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+
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