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@@ -1080,7 +1080,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
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static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
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{
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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i915_reg_t reg = PIPEDSL(pipe);
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u32 line1, line2;
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u32 line_mask;
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@@ -1116,7 +1116,7 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
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static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
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enum pipe pipe = crtc->pipe;
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@@ -1656,7 +1656,7 @@ static int intel_num_dvo_pipes(struct drm_device *dev)
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static void i9xx_enable_pll(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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i915_reg_t reg = DPLL(crtc->pipe);
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u32 dpll = crtc->config->dpll_hw_state.dpll;
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@@ -1728,7 +1728,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
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static void i9xx_disable_pll(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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enum pipe pipe = crtc->pipe;
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/* Disable DVO 2x clock on both PLLs if necessary */
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@@ -1980,7 +1980,7 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
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static void intel_enable_pipe(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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enum pipe pipe = crtc->pipe;
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enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
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enum pipe pch_transcoder;
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@@ -2053,7 +2053,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
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*/
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static void intel_disable_pipe(struct intel_crtc *crtc)
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{
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- struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
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enum pipe pipe = crtc->pipe;
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i915_reg_t reg;
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@@ -2264,7 +2264,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
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unsigned int rotation)
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{
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struct drm_device *dev = fb->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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struct i915_ggtt_view view;
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u32 alignment;
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@@ -2566,7 +2566,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
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struct intel_initial_plane_config *plane_config)
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{
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struct drm_device *dev = intel_crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_crtc *c;
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struct intel_crtc *i;
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struct drm_i915_gem_object *obj;
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@@ -2662,7 +2662,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
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const struct intel_plane_state *plane_state)
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{
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struct drm_device *dev = primary->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_framebuffer *fb = plane_state->base.fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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@@ -2775,7 +2775,7 @@ static void i9xx_disable_primary_plane(struct drm_plane *primary,
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struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int plane = intel_crtc->plane;
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@@ -2792,7 +2792,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
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const struct intel_plane_state *plane_state)
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{
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struct drm_device *dev = primary->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_framebuffer *fb = plane_state->base.fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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@@ -2920,7 +2920,7 @@ u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
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static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
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{
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struct drm_device *dev = intel_crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
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I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
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@@ -3030,7 +3030,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
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const struct intel_plane_state *plane_state)
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{
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struct drm_device *dev = plane->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_framebuffer *fb = plane_state->base.fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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@@ -3114,7 +3114,7 @@ static void skylake_disable_primary_plane(struct drm_plane *primary,
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struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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int pipe = to_intel_crtc(crtc)->pipe;
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I915_WRITE(PLANE_CTL(pipe, 0), 0);
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@@ -3250,7 +3250,7 @@ static void intel_update_pipe_config(struct intel_crtc *crtc,
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struct intel_crtc_state *old_crtc_state)
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{
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struct drm_device *dev = crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc_state *pipe_config =
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to_intel_crtc_state(crtc->base.state);
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@@ -3291,7 +3291,7 @@ static void intel_update_pipe_config(struct intel_crtc *crtc,
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static void intel_fdi_normal_train(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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i915_reg_t reg;
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@@ -3334,7 +3334,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
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static void ironlake_fdi_link_train(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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i915_reg_t reg;
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@@ -3435,7 +3435,7 @@ static const int snb_b_fdi_train_param[] = {
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static void gen6_fdi_link_train(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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i915_reg_t reg;
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@@ -3568,7 +3568,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
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static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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i915_reg_t reg;
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@@ -3687,7 +3687,7 @@ train_done:
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static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
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{
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struct drm_device *dev = intel_crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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int pipe = intel_crtc->pipe;
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i915_reg_t reg;
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u32 temp;
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@@ -3724,7 +3724,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
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static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
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{
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struct drm_device *dev = intel_crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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int pipe = intel_crtc->pipe;
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i915_reg_t reg;
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u32 temp;
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@@ -3754,7 +3754,7 @@ static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
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static void ironlake_fdi_disable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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i915_reg_t reg;
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@@ -3850,7 +3850,7 @@ static void page_flip_completed(struct intel_crtc *intel_crtc)
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static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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long ret;
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WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
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@@ -4013,7 +4013,7 @@ static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
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enum pipe pch_transcoder)
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{
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struct drm_device *dev = crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
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I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
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@@ -4035,7 +4035,7 @@ static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
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static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
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{
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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uint32_t temp;
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temp = I915_READ(SOUTH_CHICKEN1);
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@@ -4104,7 +4104,7 @@ intel_trans_dp_port_sel(struct drm_crtc *crtc)
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static void ironlake_pch_enable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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u32 temp;
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@@ -4194,7 +4194,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
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static void lpt_pch_enable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
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@@ -4210,7 +4210,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
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static void cpt_verify_modeset(struct drm_device *dev, int pipe)
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{
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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i915_reg_t dslreg = PIPEDSL(pipe);
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u32 temp;
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@@ -4388,7 +4388,7 @@ static void skylake_scaler_disable(struct intel_crtc *crtc)
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static void skylake_pfit_enable(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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int pipe = crtc->pipe;
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struct intel_crtc_scaler_state *scaler_state =
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&crtc->config->scaler_state;
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@@ -4416,7 +4416,7 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
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static void ironlake_pfit_enable(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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int pipe = crtc->pipe;
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if (crtc->config->pch_pfit.enabled) {
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@@ -4437,7 +4437,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
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void hsw_enable_ips(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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if (!crtc->config->ips_enabled)
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return;
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@@ -4475,7 +4475,7 @@ void hsw_enable_ips(struct intel_crtc *crtc)
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void hsw_disable_ips(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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if (!crtc->config->ips_enabled)
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return;
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@@ -4503,7 +4503,7 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
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{
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if (intel_crtc->overlay) {
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struct drm_device *dev = intel_crtc->base.dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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mutex_lock(&dev->struct_mutex);
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dev_priv->mm.interruptible = false;
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@@ -4531,7 +4531,7 @@ static void
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intel_post_enable_primary(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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@@ -4563,7 +4563,7 @@ static void
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intel_pre_disable_primary(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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@@ -4590,7 +4590,7 @@ static void
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intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
|
|
|
|
|
@@ -4649,7 +4649,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
|
|
|
{
|
|
|
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc_state *pipe_config =
|
|
|
to_intel_crtc_state(crtc->base.state);
|
|
|
struct drm_atomic_state *old_state = old_crtc_state->base.state;
|
|
@@ -4752,7 +4752,7 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask
|
|
|
static void ironlake_crtc_enable(struct drm_crtc *crtc)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
struct intel_encoder *encoder;
|
|
|
int pipe = intel_crtc->pipe;
|
|
@@ -4849,7 +4849,7 @@ static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
|
|
|
static void haswell_crtc_enable(struct drm_crtc *crtc)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
struct intel_encoder *encoder;
|
|
|
int pipe = intel_crtc->pipe, hsw_workaround_pipe;
|
|
@@ -4973,7 +4973,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
|
|
|
static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
int pipe = crtc->pipe;
|
|
|
|
|
|
/* To avoid upsetting the power well on haswell only disable the pfit if
|
|
@@ -4988,7 +4988,7 @@ static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
|
|
|
static void ironlake_crtc_disable(struct drm_crtc *crtc)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
struct intel_encoder *encoder;
|
|
|
int pipe = intel_crtc->pipe;
|
|
@@ -5051,7 +5051,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
|
|
|
static void haswell_crtc_disable(struct drm_crtc *crtc)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
struct intel_encoder *encoder;
|
|
|
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
|
|
@@ -5103,7 +5103,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
|
|
|
static void i9xx_pfit_enable(struct intel_crtc *crtc)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc_state *pipe_config = crtc->config;
|
|
|
|
|
|
if (!pipe_config->gmch_pfit.control)
|
|
@@ -5255,7 +5255,7 @@ static unsigned long
|
|
|
modeset_get_crtc_power_domains(struct drm_crtc *crtc,
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = crtc->dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
enum intel_display_power_domain domain;
|
|
|
unsigned long domains, new_domains, old_domains;
|
|
@@ -5300,7 +5300,7 @@ static int skl_calc_cdclk(int max_pixclk, int vco);
|
|
|
|
|
|
static void intel_update_max_cdclk(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
|
|
if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
|
|
|
u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
|
|
@@ -5361,7 +5361,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
|
|
|
|
|
|
static void intel_update_cdclk(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
|
|
dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
|
|
|
|
|
@@ -5887,7 +5887,7 @@ sanitize:
|
|
|
/* Adjust CDclk dividers to allow high res or save power if possible */
|
|
|
static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
u32 val, cmd;
|
|
|
|
|
|
WARN_ON(dev_priv->display.get_display_clock_speed(dev)
|
|
@@ -5952,7 +5952,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
|
|
|
|
|
|
static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
u32 val, cmd;
|
|
|
|
|
|
WARN_ON(dev_priv->display.get_display_clock_speed(dev)
|
|
@@ -6040,7 +6040,7 @@ static int intel_mode_max_pixclk(struct drm_device *dev,
|
|
|
struct drm_atomic_state *state)
|
|
|
{
|
|
|
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct drm_crtc *crtc;
|
|
|
struct drm_crtc_state *crtc_state;
|
|
|
unsigned max_pixclk = 0, i;
|
|
@@ -6067,7 +6067,7 @@ static int intel_mode_max_pixclk(struct drm_device *dev,
|
|
|
static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
|
|
|
{
|
|
|
struct drm_device *dev = state->dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
int max_pixclk = intel_mode_max_pixclk(dev, state);
|
|
|
struct intel_atomic_state *intel_state =
|
|
|
to_intel_atomic_state(state);
|
|
@@ -6135,7 +6135,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
|
|
|
static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
|
|
|
{
|
|
|
struct drm_device *dev = old_state->dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_atomic_state *old_intel_state =
|
|
|
to_intel_atomic_state(old_state);
|
|
|
unsigned req_cdclk = old_intel_state->dev_cdclk;
|
|
@@ -6181,7 +6181,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
|
|
|
intel_set_pipe_src_size(intel_crtc);
|
|
|
|
|
|
if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
|
|
I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
|
|
|
I915_WRITE(CHV_CANVAS(pipe), 0);
|
|
@@ -6226,7 +6226,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
|
|
|
static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
|
|
I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
|
|
|
I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
|
|
@@ -6283,7 +6283,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
|
|
|
static void i9xx_pfit_disable(struct intel_crtc *crtc)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
|
|
if (!crtc->config->gmch_pfit.control)
|
|
|
return;
|
|
@@ -6298,7 +6298,7 @@ static void i9xx_pfit_disable(struct intel_crtc *crtc)
|
|
|
static void i9xx_crtc_disable(struct drm_crtc *crtc)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
struct intel_encoder *encoder;
|
|
|
int pipe = intel_crtc->pipe;
|
|
@@ -6642,7 +6642,7 @@ static void hsw_compute_ips_config(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
|
|
pipe_config->ips_enabled = i915.enable_ips &&
|
|
|
hsw_crtc_supports_ips(crtc) &&
|
|
@@ -6662,7 +6662,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
|
|
int clock_limit = dev_priv->max_dotclk_freq;
|
|
|
|
|
@@ -6812,7 +6812,7 @@ static int broxton_get_display_clock_speed(struct drm_device *dev)
|
|
|
|
|
|
static int broadwell_get_display_clock_speed(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
uint32_t lcpll = I915_READ(LCPLL_CTL);
|
|
|
uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
|
|
|
|
|
@@ -6832,7 +6832,7 @@ static int broadwell_get_display_clock_speed(struct drm_device *dev)
|
|
|
|
|
|
static int haswell_get_display_clock_speed(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
uint32_t lcpll = I915_READ(LCPLL_CTL);
|
|
|
uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
|
|
|
|
|
@@ -6966,7 +6966,7 @@ static int i830_get_display_clock_speed(struct drm_device *dev)
|
|
|
|
|
|
static unsigned int intel_hpll_vco(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
static const unsigned int blb_vco[8] = {
|
|
|
[0] = 3200000,
|
|
|
[1] = 4000000,
|
|
@@ -7246,7 +7246,7 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
|
|
|
struct intel_link_m_n *m_n)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
int pipe = crtc->pipe;
|
|
|
|
|
|
I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
|
|
@@ -7260,7 +7260,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
|
|
|
struct intel_link_m_n *m2_n2)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
int pipe = crtc->pipe;
|
|
|
enum transcoder transcoder = crtc->config->cpu_transcoder;
|
|
|
|
|
@@ -7351,7 +7351,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
|
|
|
const struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
enum pipe pipe = crtc->pipe;
|
|
|
u32 mdiv;
|
|
|
u32 bestn, bestm1, bestm2, bestp1, bestp2;
|
|
@@ -7451,7 +7451,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
|
|
|
const struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
enum pipe pipe = crtc->pipe;
|
|
|
enum dpio_channel port = vlv_pipe_to_channel(pipe);
|
|
|
u32 loopfilter, tribuf_calcntr;
|
|
@@ -7613,7 +7613,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
|
|
|
struct dpll *reduced_clock)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
u32 dpll;
|
|
|
bool is_sdvo;
|
|
|
struct dpll *clock = &crtc_state->dpll;
|
|
@@ -7689,7 +7689,7 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
|
|
|
struct dpll *reduced_clock)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
u32 dpll;
|
|
|
struct dpll *clock = &crtc_state->dpll;
|
|
|
|
|
@@ -7724,7 +7724,7 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
|
|
|
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
|
|
|
{
|
|
|
struct drm_device *dev = intel_crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
|
|
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
|
|
|
const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
|
|
@@ -7786,7 +7786,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
|
|
|
static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
|
|
|
{
|
|
|
struct drm_device *dev = intel_crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
|
|
|
|
|
/* pipesrc controls the size that is scaled from, which should
|
|
@@ -7801,7 +7801,7 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
|
|
|
uint32_t tmp;
|
|
|
|
|
@@ -7836,7 +7836,7 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
u32 tmp;
|
|
|
|
|
|
tmp = I915_READ(PIPESRC(crtc->pipe));
|
|
@@ -7874,7 +7874,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
|
|
|
static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
|
|
|
{
|
|
|
struct drm_device *dev = intel_crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
uint32_t pipeconf;
|
|
|
|
|
|
pipeconf = 0;
|
|
@@ -7939,7 +7939,7 @@ static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
const struct intel_limit *limit;
|
|
|
int refclk = 48000;
|
|
|
|
|
@@ -7975,7 +7975,7 @@ static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
const struct intel_limit *limit;
|
|
|
int refclk = 96000;
|
|
|
|
|
@@ -8018,7 +8018,7 @@ static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
const struct intel_limit *limit;
|
|
|
int refclk = 96000;
|
|
|
|
|
@@ -8052,7 +8052,7 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
const struct intel_limit *limit;
|
|
|
int refclk = 96000;
|
|
|
|
|
@@ -8128,7 +8128,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
uint32_t tmp;
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
|
|
@@ -8155,7 +8155,7 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
int pipe = pipe_config->cpu_transcoder;
|
|
|
struct dpll clock;
|
|
|
u32 mdiv;
|
|
@@ -8183,7 +8183,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
|
|
|
struct intel_initial_plane_config *plane_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
u32 val, base, offset;
|
|
|
int pipe = crtc->pipe, plane = crtc->plane;
|
|
|
int fourcc, pixel_format;
|
|
@@ -8251,7 +8251,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
int pipe = pipe_config->cpu_transcoder;
|
|
|
enum dpio_channel port = vlv_pipe_to_channel(pipe);
|
|
|
struct dpll clock;
|
|
@@ -8285,7 +8285,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
enum intel_display_power_domain power_domain;
|
|
|
uint32_t tmp;
|
|
|
bool ret;
|
|
@@ -8396,7 +8396,7 @@ out:
|
|
|
|
|
|
static void ironlake_init_pch_refclk(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_encoder *encoder;
|
|
|
int i;
|
|
|
u32 val, final;
|
|
@@ -8667,7 +8667,7 @@ static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
|
|
|
static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
|
|
|
bool with_fdi)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
uint32_t reg, tmp;
|
|
|
|
|
|
if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
|
|
@@ -8706,7 +8706,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
|
|
|
/* Sequence to disable CLKOUT_DP */
|
|
|
static void lpt_disable_clkout_dp(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
uint32_t reg, tmp;
|
|
|
|
|
|
mutex_lock(&dev_priv->sb_lock);
|
|
@@ -8827,7 +8827,7 @@ void intel_init_pch_refclk(struct drm_device *dev)
|
|
|
|
|
|
static void ironlake_set_pipeconf(struct drm_crtc *crtc)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = crtc->dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
int pipe = intel_crtc->pipe;
|
|
|
uint32_t val;
|
|
@@ -8869,7 +8869,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
|
|
|
|
|
|
static void haswell_set_pipeconf(struct drm_crtc *crtc)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = crtc->dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
|
|
|
u32 val = 0;
|
|
@@ -8888,7 +8888,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
|
|
|
|
|
|
static void haswell_set_pipemisc(struct drm_crtc *crtc)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = crtc->dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
|
|
if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
|
|
@@ -8941,7 +8941,7 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
|
|
|
{
|
|
|
struct drm_crtc *crtc = &intel_crtc->base;
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct drm_atomic_state *state = crtc_state->base.state;
|
|
|
struct drm_connector *connector;
|
|
|
struct drm_connector_state *connector_state;
|
|
@@ -9044,7 +9044,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct dpll reduced_clock;
|
|
|
bool has_reduced_clock = false;
|
|
|
struct intel_shared_dpll *pll;
|
|
@@ -9110,7 +9110,7 @@ static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
|
|
|
struct intel_link_m_n *m_n)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
enum pipe pipe = crtc->pipe;
|
|
|
|
|
|
m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
|
|
@@ -9128,7 +9128,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
|
|
|
struct intel_link_m_n *m2_n2)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
enum pipe pipe = crtc->pipe;
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 5) {
|
|
@@ -9186,7 +9186,7 @@ static void skylake_get_pfit_config(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
|
|
|
uint32_t ps_ctrl = 0;
|
|
|
int id = -1;
|
|
@@ -9217,7 +9217,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
|
|
|
struct intel_initial_plane_config *plane_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
u32 val, base, offset, stride_mult, tiling;
|
|
|
int pipe = crtc->pipe;
|
|
|
int fourcc, pixel_format;
|
|
@@ -9300,7 +9300,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
uint32_t tmp;
|
|
|
|
|
|
tmp = I915_READ(PF_CTL(crtc->pipe));
|
|
@@ -9325,7 +9325,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
|
|
|
struct intel_initial_plane_config *plane_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
u32 val, base, offset;
|
|
|
int pipe = crtc->pipe;
|
|
|
int fourcc, pixel_format;
|
|
@@ -9393,7 +9393,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
enum intel_display_power_domain power_domain;
|
|
|
uint32_t tmp;
|
|
|
bool ret;
|
|
@@ -9723,7 +9723,7 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
|
|
|
static int ilk_max_pixel_rate(struct drm_atomic_state *state)
|
|
|
{
|
|
|
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
|
|
|
- struct drm_i915_private *dev_priv = state->dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
|
|
|
struct drm_crtc *crtc;
|
|
|
struct drm_crtc_state *cstate;
|
|
|
struct intel_crtc_state *crtc_state;
|
|
@@ -9759,7 +9759,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
|
|
|
|
|
|
static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
uint32_t val, data;
|
|
|
int ret;
|
|
|
|
|
@@ -10041,7 +10041,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
|
|
|
unsigned long *power_domain_mask)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
enum intel_display_power_domain power_domain;
|
|
|
u32 tmp;
|
|
|
|
|
@@ -10092,7 +10092,7 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
|
|
|
unsigned long *power_domain_mask)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
enum intel_display_power_domain power_domain;
|
|
|
enum port port;
|
|
|
enum transcoder cpu_transcoder;
|
|
@@ -10142,7 +10142,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_shared_dpll *pll;
|
|
|
enum port port;
|
|
|
uint32_t tmp;
|
|
@@ -10185,7 +10185,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
enum intel_display_power_domain power_domain;
|
|
|
unsigned long power_domain_mask;
|
|
|
bool active;
|
|
@@ -10261,7 +10261,7 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
|
|
|
const struct intel_plane_state *plane_state)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
uint32_t cntl = 0, size = 0;
|
|
|
|
|
@@ -10324,7 +10324,7 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
|
|
|
const struct intel_plane_state *plane_state)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
int pipe = intel_crtc->pipe;
|
|
|
uint32_t cntl = 0;
|
|
@@ -10372,7 +10372,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
|
|
|
const struct intel_plane_state *plane_state)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
int pipe = intel_crtc->pipe;
|
|
|
u32 base = intel_crtc->cursor_addr;
|
|
@@ -10539,7 +10539,7 @@ mode_fits_in_fbdev(struct drm_device *dev,
|
|
|
struct drm_display_mode *mode)
|
|
|
{
|
|
|
#ifdef CONFIG_DRM_FBDEV_EMULATION
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
struct drm_framebuffer *fb;
|
|
|
|
|
@@ -10809,7 +10809,7 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
|
|
|
static int i9xx_pll_refclk(struct drm_device *dev,
|
|
|
const struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
u32 dpll = pipe_config->dpll_hw_state.dpll;
|
|
|
|
|
|
if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
|
|
@@ -10827,7 +10827,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
int pipe = pipe_config->cpu_transcoder;
|
|
|
u32 dpll = pipe_config->dpll_hw_state.dpll;
|
|
|
u32 fp;
|
|
@@ -10953,7 +10953,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
|
|
|
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
|
|
|
struct drm_crtc *crtc)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
|
|
|
struct drm_display_mode *mode;
|
|
@@ -11066,7 +11066,7 @@ static bool __pageflip_finished_cs(struct intel_crtc *crtc,
|
|
|
struct intel_flip_work *work)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
unsigned reset_counter;
|
|
|
|
|
|
reset_counter = i915_reset_counter(&dev_priv->gpu_error);
|
|
@@ -11277,7 +11277,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
|
|
|
uint32_t flags)
|
|
|
{
|
|
|
struct intel_engine_cs *engine = req->engine;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
uint32_t pf, pipesrc;
|
|
|
int ret;
|
|
@@ -11315,7 +11315,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
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|
|
uint32_t flags)
|
|
|
{
|
|
|
struct intel_engine_cs *engine = req->engine;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
uint32_t pf, pipesrc;
|
|
|
int ret;
|
|
@@ -11474,7 +11474,7 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
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|
|
struct intel_flip_work *work)
|
|
|
{
|
|
|
struct drm_device *dev = intel_crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
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|
|
const enum pipe pipe = intel_crtc->pipe;
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|
|
u32 ctl, stride, tile_height;
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|
@@ -11526,7 +11526,7 @@ static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
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|
struct intel_flip_work *work)
|
|
|
{
|
|
|
struct drm_device *dev = intel_crtc->base.dev;
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|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
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|
|
struct intel_framebuffer *intel_fb =
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|
|
to_intel_framebuffer(intel_crtc->base.primary->fb);
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|
struct drm_i915_gem_object *obj = intel_fb->obj;
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|
@@ -11662,7 +11662,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
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|
|
uint32_t page_flip_flags)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->dev;
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|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
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|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct drm_framebuffer *old_fb = crtc->primary->fb;
|
|
|
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
@@ -12099,7 +12099,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
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|
|
struct drm_crtc_state *crtc_state)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
struct intel_crtc_state *pipe_config =
|
|
|
to_intel_crtc_state(crtc_state);
|
|
@@ -12960,7 +12960,7 @@ static void verify_wm_state(struct drm_crtc *crtc,
|
|
|
struct drm_crtc_state *new_state)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct skl_ddb_allocation hw_ddb, *sw_ddb;
|
|
|
struct skl_ddb_entry *hw_entry, *sw_entry;
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
@@ -13066,7 +13066,7 @@ verify_crtc_state(struct drm_crtc *crtc,
|
|
|
struct drm_crtc_state *new_crtc_state)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_encoder *encoder;
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
struct intel_crtc_state *pipe_config, *sw_config;
|
|
@@ -13189,7 +13189,7 @@ verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
|
|
|
struct drm_crtc_state *old_crtc_state,
|
|
|
struct drm_crtc_state *new_crtc_state)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
|
|
|
struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
|
|
|
|
|
@@ -13228,7 +13228,7 @@ intel_modeset_verify_crtc(struct drm_crtc *crtc,
|
|
|
static void
|
|
|
verify_disabled_dpll_state(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
int i;
|
|
|
|
|
|
for (i = 0; i < dev_priv->num_shared_dpll; i++)
|
|
@@ -13410,7 +13410,7 @@ static int intel_modeset_all_pipes(struct drm_atomic_state *state)
|
|
|
static int intel_modeset_checks(struct drm_atomic_state *state)
|
|
|
{
|
|
|
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
|
|
|
- struct drm_i915_private *dev_priv = state->dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
|
|
|
struct drm_crtc *crtc;
|
|
|
struct drm_crtc_state *crtc_state;
|
|
|
int ret = 0, i;
|
|
@@ -13576,7 +13576,7 @@ static int intel_atomic_prepare_commit(struct drm_device *dev,
|
|
|
struct drm_atomic_state *state,
|
|
|
bool nonblock)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct drm_plane_state *plane_state;
|
|
|
struct drm_crtc_state *crtc_state;
|
|
|
struct drm_plane *plane;
|
|
@@ -13705,7 +13705,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
|
|
|
{
|
|
|
struct drm_device *dev = state->dev;
|
|
|
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct drm_crtc_state *old_crtc_state;
|
|
|
struct drm_crtc *crtc;
|
|
|
struct intel_crtc_state *intel_cstate;
|
|
@@ -13937,7 +13937,7 @@ static int intel_atomic_commit(struct drm_device *dev,
|
|
|
bool nonblock)
|
|
|
{
|
|
|
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
int ret = 0;
|
|
|
|
|
|
if (intel_state->modeset && nonblock) {
|
|
@@ -14542,7 +14542,7 @@ static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_cr
|
|
|
|
|
|
static void intel_crtc_init(struct drm_device *dev, int pipe)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_crtc *intel_crtc;
|
|
|
struct intel_crtc_state *crtc_state = NULL;
|
|
|
struct drm_plane *primary = NULL;
|
|
@@ -14669,7 +14669,7 @@ static int intel_encoder_clones(struct intel_encoder *encoder)
|
|
|
|
|
|
static bool has_edp_a(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
|
|
if (!IS_MOBILE(dev))
|
|
|
return false;
|
|
@@ -14685,7 +14685,7 @@ static bool has_edp_a(struct drm_device *dev)
|
|
|
|
|
|
static bool intel_crt_present(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 9)
|
|
|
return false;
|
|
@@ -14711,7 +14711,7 @@ static bool intel_crt_present(struct drm_device *dev)
|
|
|
|
|
|
static void intel_setup_outputs(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
struct intel_encoder *encoder;
|
|
|
bool dpd_is_edp = false;
|
|
|
|
|
@@ -15364,7 +15364,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
|
|
|
*/
|
|
|
static void quirk_pipea_force(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
|
|
dev_priv->quirks |= QUIRK_PIPEA_FORCE;
|
|
|
DRM_INFO("applying pipe a force quirk\n");
|
|
@@ -15372,7 +15372,7 @@ static void quirk_pipea_force(struct drm_device *dev)
|
|
|
|
|
|
static void quirk_pipeb_force(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
|
|
dev_priv->quirks |= QUIRK_PIPEB_FORCE;
|
|
|
DRM_INFO("applying pipe b force quirk\n");
|
|
@@ -15383,7 +15383,7 @@ static void quirk_pipeb_force(struct drm_device *dev)
|
|
|
*/
|
|
|
static void quirk_ssc_force_disable(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
|
|
|
DRM_INFO("applying lvds SSC disable quirk\n");
|
|
|
}
|
|
@@ -15394,7 +15394,7 @@ static void quirk_ssc_force_disable(struct drm_device *dev)
|
|
|
*/
|
|
|
static void quirk_invert_brightness(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
|
|
|
DRM_INFO("applying inverted panel brightness quirk\n");
|
|
|
}
|
|
@@ -15402,7 +15402,7 @@ static void quirk_invert_brightness(struct drm_device *dev)
|
|
|
/* Some VBT's incorrectly indicate no backlight is present */
|
|
|
static void quirk_backlight_present(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
|
|
|
DRM_INFO("applying backlight present quirk\n");
|
|
|
}
|
|
@@ -15528,7 +15528,7 @@ static void intel_init_quirks(struct drm_device *dev)
|
|
|
/* Disable the VGA plane that we never use */
|
|
|
static void i915_disable_vga(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
u8 sr1;
|
|
|
i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
|
|
|
|
|
@@ -15546,7 +15546,7 @@ static void i915_disable_vga(struct drm_device *dev)
|
|
|
|
|
|
void intel_modeset_init_hw(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
|
|
intel_update_cdclk(dev);
|
|
|
|
|
@@ -15794,7 +15794,7 @@ static bool
|
|
|
intel_check_plane_mapping(struct intel_crtc *crtc)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
u32 val;
|
|
|
|
|
|
if (INTEL_INFO(dev)->num_pipes == 1)
|
|
@@ -15834,7 +15834,7 @@ static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
|
|
|
static void intel_sanitize_crtc(struct intel_crtc *crtc)
|
|
|
{
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
|
|
|
|
|
|
/* Clear any frame start delays used for debugging left by the BIOS */
|
|
@@ -15959,7 +15959,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
|
|
|
|
|
|
void i915_redisable_vga_power_on(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
|
|
|
|
|
|
if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
|
|
@@ -15970,7 +15970,7 @@ void i915_redisable_vga_power_on(struct drm_device *dev)
|
|
|
|
|
|
void i915_redisable_vga(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
|
|
/* This function can be called both from intel_modeset_setup_hw_state or
|
|
|
* at a very early point in our resume sequence, where the power well
|
|
@@ -16010,7 +16010,7 @@ static void readout_plane_state(struct intel_crtc *crtc)
|
|
|
|
|
|
static void intel_modeset_readout_hw_state(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
enum pipe pipe;
|
|
|
struct intel_crtc *crtc;
|
|
|
struct intel_encoder *encoder;
|
|
@@ -16163,7 +16163,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
|
|
|
static void
|
|
|
intel_modeset_setup_hw_state(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
enum pipe pipe;
|
|
|
struct intel_crtc *crtc;
|
|
|
struct intel_encoder *encoder;
|
|
@@ -16346,7 +16346,7 @@ void intel_connector_unregister(struct drm_connector *connector)
|
|
|
|
|
|
void intel_modeset_cleanup(struct drm_device *dev)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
|
|
intel_disable_gt_powersave(dev_priv);
|
|
|
|
|
@@ -16392,7 +16392,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector,
|
|
|
*/
|
|
|
int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
|
|
|
u16 gmch_ctrl;
|
|
|
|
|
@@ -16548,7 +16548,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
|
|
|
struct drm_device *dev,
|
|
|
struct intel_display_error_state *error)
|
|
|
{
|
|
|
- struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
+ struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
int i;
|
|
|
|
|
|
if (!error)
|