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@@ -988,6 +988,36 @@ static int i965_do_reset(struct drm_device *dev)
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return 0;
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}
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+static int g4x_do_reset(struct drm_device *dev)
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+{
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+ int ret;
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+
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+ pci_write_config_byte(dev->pdev, I965_GDRST,
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+ GRDOM_RENDER | GRDOM_RESET_ENABLE);
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+ ret = wait_for(i965_reset_complete(dev), 500);
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+ if (ret)
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+ return ret;
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+
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+ /* WaVcpClkGateDisableForMediaReset:ctg,elk */
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+ I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
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+ POSTING_READ(VDECCLK_GATE_D);
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+
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+ pci_write_config_byte(dev->pdev, I965_GDRST,
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+ GRDOM_MEDIA | GRDOM_RESET_ENABLE);
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+ ret = wait_for(i965_reset_complete(dev), 500);
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+ if (ret)
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+ return ret;
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+
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+ /* WaVcpClkGateDisableForMediaReset:ctg,elk */
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+ I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
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+ POSTING_READ(VDECCLK_GATE_D);
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+
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+ pci_write_config_byte(dev->pdev, I965_GDRST, 0);
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+
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+ return 0;
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+}
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+
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static int ironlake_do_reset(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@@ -1040,7 +1070,11 @@ int intel_gpu_reset(struct drm_device *dev)
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case 7:
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case 6: return gen6_do_reset(dev);
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case 5: return ironlake_do_reset(dev);
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- case 4: return i965_do_reset(dev);
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+ case 4:
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+ if (IS_G4X(dev))
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+ return g4x_do_reset(dev);
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+ else
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+ return i965_do_reset(dev);
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default: return -ENODEV;
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}
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}
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