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@@ -2290,8 +2290,9 @@ void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
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*/
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/* set the PLL on, remove the HNP/SRP and set the PHY */
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+ val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
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writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
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- (0x5 << 10), hsotg->regs + GUSBCFG);
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+ (val << 10), hsotg->regs + GUSBCFG);
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s3c_hsotg_init_fifo(hsotg);
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@@ -2978,6 +2979,7 @@ static void s3c_hsotg_phy_disable(struct dwc2_hsotg *hsotg)
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*/
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static void s3c_hsotg_init(struct dwc2_hsotg *hsotg)
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{
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+ u32 trdtim;
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/* unmask subset of endpoint interrupts */
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writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
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@@ -3002,8 +3004,10 @@ static void s3c_hsotg_init(struct dwc2_hsotg *hsotg)
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s3c_hsotg_init_fifo(hsotg);
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/* set the PLL on, remove the HNP/SRP and set the PHY */
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- writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10),
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- hsotg->regs + GUSBCFG);
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+ trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
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+ writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
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+ (trdtim << 10),
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+ hsotg->regs + GUSBCFG);
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if (using_dma(hsotg))
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__orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
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