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@@ -65,6 +65,7 @@
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#define ACPI_SIG_ECDT "ECDT" /* Embedded Controller Boot Resources Table */
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#define ACPI_SIG_EINJ "EINJ" /* Error Injection table */
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#define ACPI_SIG_ERST "ERST" /* Error Record Serialization Table */
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+#define ACPI_SIG_HMAT "HMAT" /* Heterogeneous Memory Attributes Table */
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#define ACPI_SIG_HEST "HEST" /* Hardware Error Source Table */
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#define ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */
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#define ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics Table */
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@@ -686,6 +687,122 @@ struct acpi_hest_generic_data_v300 {
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#define ACPI_HEST_GEN_VALID_FRU_STRING (1<<1)
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#define ACPI_HEST_GEN_VALID_TIMESTAMP (1<<2)
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+/*******************************************************************************
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+ *
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+ * HMAT - Heterogeneous Memory Attributes Table (ACPI 6.2)
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+ * Version 1
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+ *
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+ ******************************************************************************/
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+
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+struct acpi_table_hmat {
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+ struct acpi_table_header header; /* Common ACPI table header */
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+ u32 reserved;
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+};
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+
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+/* Values for HMAT structure types */
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+
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+enum acpi_hmat_type {
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+ ACPI_HMAT_TYPE_ADDRESS_RANGE = 0, /* Memory subystem address range */
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+ ACPI_HMAT_TYPE_LOCALITY = 1, /* System locality latency and bandwidth information */
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+ ACPI_HMAT_TYPE_CACHE = 2, /* Memory side cache information */
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+ ACPI_HMAT_TYPE_RESERVED = 3 /* 3 and greater are reserved */
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+};
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+
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+struct acpi_hmat_structure {
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+ u16 type;
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+ u16 reserved;
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+ u32 length;
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+};
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+
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+/*
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+ * HMAT Structures, correspond to Type in struct acpi_hmat_structure
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+ */
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+
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+/* 0: Memory subystem address range */
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+
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+struct acpi_hmat_address_range {
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+ struct acpi_hmat_structure header;
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+ u16 flags;
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+ u16 reserved1;
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+ u32 processor_PD; /* Processor proximity domain */
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+ u32 memory_PD; /* Memory proximity domain */
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+ u32 reserved2;
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+ u64 physical_address_base; /* Physical address range base */
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+ u64 physical_address_length; /* Physical address range length */
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+};
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+
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+/* Masks for Flags field above */
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+
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+#define ACPI_HMAT_PROCESSOR_PD_VALID (1) /* 1: processor_PD field is valid */
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+#define ACPI_HMAT_MEMORY_PD_VALID (1<<1) /* 1: memory_PD field is valid */
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+#define ACPI_HMAT_RESERVATION_HINT (1<<2) /* 1: Reservation hint */
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+
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+/* 1: System locality latency and bandwidth information */
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+
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+struct acpi_hmat_locality {
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+ struct acpi_hmat_structure header;
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+ u8 flags;
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+ u8 data_type;
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+ u16 reserved1;
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+ u32 number_of_initiator_Pds;
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+ u32 number_of_target_Pds;
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+ u32 reserved2;
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+ u64 entry_base_unit;
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+};
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+
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+/* Masks for Flags field above */
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+
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+#define ACPI_HMAT_MEMORY_HIERARCHY (0x0F)
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+
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+/* Values for Memory Hierarchy flag */
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+
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+#define ACPI_HMAT_MEMORY 0
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+#define ACPI_HMAT_LAST_LEVEL_CACHE 1
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+#define ACPI_HMAT_1ST_LEVEL_CACHE 2
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+#define ACPI_HMAT_2ND_LEVEL_CACHE 3
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+#define ACPI_HMAT_3RD_LEVEL_CACHE 4
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+
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+/* Values for data_type field above */
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+
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+#define ACPI_HMAT_ACCESS_LATENCY 0
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+#define ACPI_HMAT_READ_LATENCY 1
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+#define ACPI_HMAT_WRITE_LATENCY 2
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+#define ACPI_HMAT_ACCESS_BANDWIDTH 3
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+#define ACPI_HMAT_READ_BANDWIDTH 4
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+#define ACPI_HMAT_WRITE_BANDWIDTH 5
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+
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+/* 2: Memory side cache information */
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+
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+struct acpi_hmat_cache {
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+ struct acpi_hmat_structure header;
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+ u32 memory_PD;
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+ u32 reserved1;
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+ u64 cache_size;
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+ u32 cache_attributes;
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+ u16 reserved2;
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+ u16 number_of_SMBIOShandles;
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+};
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+
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+/* Masks for cache_attributes field above */
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+
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+#define ACPI_HMAT_TOTAL_CACHE_LEVEL (0x0000000F)
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+#define ACPI_HMAT_CACHE_LEVEL (0x000000F0)
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+#define ACPI_HMAT_CACHE_ASSOCIATIVITY (0x00000F00)
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+#define ACPI_HMAT_WRITE_POLICY (0x0000F000)
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+#define ACPI_HMAT_CACHE_LINE_SIZE (0xFFFF0000)
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+
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+/* Values for cache associativity flag */
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+
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+#define ACPI_HMAT_CA_NONE (0)
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+#define ACPI_HMAT_CA_DIRECT_MAPPED (1)
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+#define ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING (2)
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+
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+/* Values for write policy flag */
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+
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+#define ACPI_HMAT_CP_NONE (0)
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+#define ACPI_HMAT_CP_WB (1)
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+#define ACPI_HMAT_CP_WT (2)
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+
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/*******************************************************************************
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*
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* MADT - Multiple APIC Description Table
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