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@@ -14,11 +14,13 @@
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*
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*/
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+#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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+#include <linux/reboot.h>
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#include <linux/rtc.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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@@ -28,6 +30,8 @@
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#define JZ_REG_RTC_SEC_ALARM 0x08
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#define JZ_REG_RTC_REGULATOR 0x0C
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#define JZ_REG_RTC_HIBERNATE 0x20
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+#define JZ_REG_RTC_WAKEUP_FILTER 0x24
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+#define JZ_REG_RTC_RESET_COUNTER 0x28
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#define JZ_REG_RTC_SCRATCHPAD 0x34
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/* The following are present on the jz4780 */
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@@ -45,6 +49,9 @@
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/* Magic value to enable writes on jz4780 */
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#define JZ_RTC_WENR_MAGIC 0xA55A
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+#define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0
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+#define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0
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+
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enum jz4740_rtc_type {
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ID_JZ4740,
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ID_JZ4780,
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@@ -55,12 +62,18 @@ struct jz4740_rtc {
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enum jz4740_rtc_type type;
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struct rtc_device *rtc;
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+ struct clk *clk;
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int irq;
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spinlock_t lock;
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+
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+ unsigned int min_wakeup_pin_assert_time;
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+ unsigned int reset_pin_assert_time;
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};
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+static struct device *dev_for_power_off;
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+
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static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
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{
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return readl(rtc->base + reg);
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@@ -246,6 +259,46 @@ void jz4740_rtc_poweroff(struct device *dev)
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}
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EXPORT_SYMBOL_GPL(jz4740_rtc_poweroff);
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+static void jz4740_rtc_power_off(void)
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+{
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+ struct jz4740_rtc *rtc = dev_get_drvdata(dev_for_power_off);
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+ unsigned long rtc_rate;
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+ unsigned long wakeup_filter_ticks;
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+ unsigned long reset_counter_ticks;
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+
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+ clk_prepare_enable(rtc->clk);
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+
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+ rtc_rate = clk_get_rate(rtc->clk);
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+
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+ /*
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+ * Set minimum wakeup pin assertion time: 100 ms.
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+ * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
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+ */
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+ wakeup_filter_ticks =
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+ (rtc->min_wakeup_pin_assert_time * rtc_rate) / 1000;
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+ if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
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+ wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
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+ else
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+ wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
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+ jz4740_rtc_reg_write(rtc,
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+ JZ_REG_RTC_WAKEUP_FILTER, wakeup_filter_ticks);
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+
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+ /*
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+ * Set reset pin low-level assertion time after wakeup: 60 ms.
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+ * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
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+ */
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+ reset_counter_ticks = (rtc->reset_pin_assert_time * rtc_rate) / 1000;
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+ if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
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+ reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
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+ else
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+ reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;
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+ jz4740_rtc_reg_write(rtc,
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+ JZ_REG_RTC_RESET_COUNTER, reset_counter_ticks);
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+
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+ jz4740_rtc_poweroff(dev_for_power_off);
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+ machine_halt();
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+}
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+
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static const struct of_device_id jz4740_rtc_of_match[] = {
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{ .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
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{ .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
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@@ -262,6 +315,7 @@ static int jz4740_rtc_probe(struct platform_device *pdev)
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const struct platform_device_id *id = platform_get_device_id(pdev);
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const struct of_device_id *of_id = of_match_device(
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jz4740_rtc_of_match, &pdev->dev);
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+ struct device_node *np = pdev->dev.of_node;
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rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
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if (!rtc)
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@@ -283,6 +337,12 @@ static int jz4740_rtc_probe(struct platform_device *pdev)
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if (IS_ERR(rtc->base))
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return PTR_ERR(rtc->base);
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+ rtc->clk = devm_clk_get(&pdev->dev, "rtc");
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+ if (IS_ERR(rtc->clk)) {
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+ dev_err(&pdev->dev, "Failed to get RTC clock\n");
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+ return PTR_ERR(rtc->clk);
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+ }
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+
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spin_lock_init(&rtc->lock);
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platform_set_drvdata(pdev, rtc);
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@@ -314,6 +374,27 @@ static int jz4740_rtc_probe(struct platform_device *pdev)
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}
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}
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+ if (np && of_device_is_system_power_controller(np)) {
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+ if (!pm_power_off) {
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+ /* Default: 60ms */
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+ rtc->reset_pin_assert_time = 60;
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+ of_property_read_u32(np, "reset-pin-assert-time-ms",
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+ &rtc->reset_pin_assert_time);
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+
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+ /* Default: 100ms */
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+ rtc->min_wakeup_pin_assert_time = 100;
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+ of_property_read_u32(np,
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+ "min-wakeup-pin-assert-time-ms",
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+ &rtc->min_wakeup_pin_assert_time);
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+
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+ dev_for_power_off = &pdev->dev;
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+ pm_power_off = jz4740_rtc_power_off;
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+ } else {
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+ dev_warn(&pdev->dev,
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+ "Poweroff handler already present!\n");
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+ }
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+ }
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+
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return 0;
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}
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