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drm/nouveau/disp: clear notify intr status when enabling, to prevent races

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs 11 years ago
parent
commit
f9895e6dbe

+ 2 - 0
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

@@ -88,12 +88,14 @@ nv50_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
 {
 {
 	struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
 	struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
 	nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000000 << index);
 	nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000000 << index);
+	nv_wr32(priv, 0x610020, 0x00000001 << index);
 }
 }
 
 
 static void
 static void
 nv50_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
 nv50_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
 {
 {
 	struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
 	struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
+	nv_wr32(priv, 0x610020, 0x00000001 << index);
 	nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000001 << index);
 	nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000001 << index);
 }
 }
 
 

+ 2 - 0
drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c

@@ -51,12 +51,14 @@ nvd0_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
 {
 {
 	struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
 	struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
 	nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000000 << index);
 	nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000000 << index);
+	nv_wr32(priv, 0x61008c, 0x00000001 << index);
 }
 }
 
 
 static void
 static void
 nvd0_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
 nvd0_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
 {
 {
 	struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
 	struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
+	nv_wr32(priv, 0x61008c, 0x00000001 << index);
 	nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000001 << index);
 	nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000001 << index);
 }
 }