|
@@ -728,6 +728,10 @@ int r100_irq_set(struct radeon_device *rdev)
|
|
tmp |= RADEON_FP2_DETECT_MASK;
|
|
tmp |= RADEON_FP2_DETECT_MASK;
|
|
}
|
|
}
|
|
WREG32(RADEON_GEN_INT_CNTL, tmp);
|
|
WREG32(RADEON_GEN_INT_CNTL, tmp);
|
|
|
|
+
|
|
|
|
+ /* read back to post the write */
|
|
|
|
+ RREG32(RADEON_GEN_INT_CNTL);
|
|
|
|
+
|
|
return 0;
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
|