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+/*
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+ * R-Car MSTP clocks
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+ *
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+ * Copyright (C) 2013 Ideas On Board SPRL
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+ *
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+ * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; version 2 of the License.
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+ */
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+
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+#include <linux/clk-provider.h>
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+#include <linux/clkdev.h>
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+#include <linux/io.h>
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+#include <linux/spinlock.h>
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+
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+/*
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+ * MSTP clocks. We can't use standard gate clocks as we need to poll on the
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+ * status register when enabling the clock.
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+ */
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+
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+#define MSTP_MAX_CLOCKS 32
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+
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+/**
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+ * struct mstp_clock_group - MSTP gating clocks group
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+ *
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+ * @data: clocks in this group
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+ * @smstpcr: module stop control register
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+ * @mstpsr: module stop status register (optional)
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+ * @lock: protects writes to SMSTPCR
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+ */
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+struct mstp_clock_group {
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+ struct clk_onecell_data data;
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+ void __iomem *smstpcr;
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+ void __iomem *mstpsr;
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+ spinlock_t lock;
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+};
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+
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+/**
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+ * struct mstp_clock - MSTP gating clock
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+ * @hw: handle between common and hardware-specific interfaces
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+ * @bit_index: control bit index
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+ * @group: MSTP clocks group
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+ */
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+struct mstp_clock {
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+ struct clk_hw hw;
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+ u32 bit_index;
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+ struct mstp_clock_group *group;
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+};
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+
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+#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
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+
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+static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
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+{
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+ struct mstp_clock *clock = to_mstp_clock(hw);
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+ struct mstp_clock_group *group = clock->group;
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+ u32 bitmask = BIT(clock->bit_index);
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+ unsigned long flags;
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+ unsigned int i;
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+ u32 value;
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+
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+ spin_lock_irqsave(&group->lock, flags);
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+
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+ value = clk_readl(group->smstpcr);
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+ if (enable)
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+ value &= ~bitmask;
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+ else
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+ value |= bitmask;
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+ clk_writel(value, group->smstpcr);
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+
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+ spin_unlock_irqrestore(&group->lock, flags);
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+
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+ if (!enable || !group->mstpsr)
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+ return 0;
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+
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+ for (i = 1000; i > 0; --i) {
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+ if (!(clk_readl(group->mstpsr) & bitmask))
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+ break;
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+ cpu_relax();
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+ }
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+
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+ if (!i) {
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+ pr_err("%s: failed to enable %p[%d]\n", __func__,
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+ group->smstpcr, clock->bit_index);
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+ return -ETIMEDOUT;
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+ }
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+
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+ return 0;
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+}
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+
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+static int cpg_mstp_clock_enable(struct clk_hw *hw)
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+{
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+ return cpg_mstp_clock_endisable(hw, true);
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+}
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+
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+static void cpg_mstp_clock_disable(struct clk_hw *hw)
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+{
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+ cpg_mstp_clock_endisable(hw, false);
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+}
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+
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+static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
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+{
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+ struct mstp_clock *clock = to_mstp_clock(hw);
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+ struct mstp_clock_group *group = clock->group;
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+ u32 value;
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+
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+ if (group->mstpsr)
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+ value = clk_readl(group->mstpsr);
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+ else
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+ value = clk_readl(group->smstpcr);
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+
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+ return !!(value & BIT(clock->bit_index));
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+}
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+
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+static const struct clk_ops cpg_mstp_clock_ops = {
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+ .enable = cpg_mstp_clock_enable,
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+ .disable = cpg_mstp_clock_disable,
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+ .is_enabled = cpg_mstp_clock_is_enabled,
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+};
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+
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+static struct clk * __init
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+cpg_mstp_clock_register(const char *name, const char *parent_name,
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+ unsigned int index, struct mstp_clock_group *group)
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+{
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+ struct clk_init_data init;
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+ struct mstp_clock *clock;
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+ struct clk *clk;
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+
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+ clock = kzalloc(sizeof(*clock), GFP_KERNEL);
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+ if (!clock) {
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+ pr_err("%s: failed to allocate MSTP clock.\n", __func__);
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+ return ERR_PTR(-ENOMEM);
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+ }
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+
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+ init.name = name;
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+ init.ops = &cpg_mstp_clock_ops;
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+ init.flags = CLK_IS_BASIC;
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+ init.parent_names = &parent_name;
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+ init.num_parents = 1;
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+
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+ clock->bit_index = index;
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+ clock->group = group;
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+ clock->hw.init = &init;
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+
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+ clk = clk_register(NULL, &clock->hw);
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+
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+ if (IS_ERR(clk))
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+ kfree(clock);
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+
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+ return clk;
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+}
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+
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+static void __init cpg_mstp_clocks_init(struct device_node *np)
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+{
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+ struct mstp_clock_group *group;
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+ struct clk **clks;
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+ unsigned int i;
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+
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+ group = kzalloc(sizeof(*group), GFP_KERNEL);
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+ clks = kzalloc(MSTP_MAX_CLOCKS * sizeof(*clks), GFP_KERNEL);
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+ if (group == NULL || clks == NULL) {
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+ kfree(group);
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+ kfree(clks);
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+ pr_err("%s: failed to allocate group\n", __func__);
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+ return;
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+ }
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+
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+ spin_lock_init(&group->lock);
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+ group->data.clks = clks;
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+
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+ group->smstpcr = of_iomap(np, 0);
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+ group->mstpsr = of_iomap(np, 1);
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+
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+ if (group->smstpcr == NULL) {
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+ pr_err("%s: failed to remap SMSTPCR\n", __func__);
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+ kfree(group);
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+ kfree(clks);
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+ return;
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+ }
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+
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+ for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
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+ const char *parent_name;
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+ const char *name;
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+ u32 clkidx;
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+ int ret;
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+
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+ /* Skip clocks with no name. */
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+ ret = of_property_read_string_index(np, "clock-output-names",
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+ i, &name);
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+ if (ret < 0 || strlen(name) == 0)
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+ continue;
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+
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+ parent_name = of_clk_get_parent_name(np, i);
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+ ret = of_property_read_u32_index(np, "renesas,clock-indices", i,
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+ &clkidx);
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+ if (parent_name == NULL || ret < 0)
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+ break;
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+
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+ if (clkidx >= MSTP_MAX_CLOCKS) {
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+ pr_err("%s: invalid clock %s %s index %u)\n",
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+ __func__, np->name, name, clkidx);
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+ continue;
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+ }
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+
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+ clks[clkidx] = cpg_mstp_clock_register(name, parent_name, i,
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+ group);
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+ if (!IS_ERR(clks[clkidx])) {
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+ group->data.clk_num = max(group->data.clk_num, clkidx);
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+ /*
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+ * Register a clkdev to let board code retrieve the
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+ * clock by name and register aliases for non-DT
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+ * devices.
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+ *
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+ * FIXME: Remove this when all devices that require a
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+ * clock will be instantiated from DT.
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+ */
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+ clk_register_clkdev(clks[clkidx], name, NULL);
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+ } else {
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+ pr_err("%s: failed to register %s %s clock (%ld)\n",
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+ __func__, np->name, name, PTR_ERR(clks[clkidx]));
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+ }
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+ }
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+
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+ of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
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+}
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+CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
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