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@@ -274,24 +274,14 @@ static int vce_v2_0_start(struct amdgpu_device *adev)
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static int vce_v2_0_stop(struct amdgpu_device *adev)
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{
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- int i, j;
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+ int i;
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int status;
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if (vce_v2_0_lmi_clean(adev)) {
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DRM_INFO("vce is not idle \n");
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return 0;
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}
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-/*
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- for (i = 0; i < 10; ++i) {
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- for (j = 0; j < 100; ++j) {
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- status = RREG32(mmVCE_FW_REG_STATUS);
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- if (!(status & 1))
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- break;
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- mdelay(1);
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- }
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- break;
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- }
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-*/
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+
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if (vce_v2_0_wait_for_idle(adev)) {
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DRM_INFO("VCE is busy, Can't set clock gateing");
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return 0;
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@@ -300,14 +290,11 @@ static int vce_v2_0_stop(struct amdgpu_device *adev)
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/* Stall UMC and register bus before resetting VCPU */
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WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8));
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- for (i = 0; i < 10; ++i) {
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- for (j = 0; j < 100; ++j) {
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- status = RREG32(mmVCE_LMI_STATUS);
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- if (status & 0x240)
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- break;
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- mdelay(1);
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- }
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- break;
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+ for (i = 0; i < 100; ++i) {
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+ status = RREG32(mmVCE_LMI_STATUS);
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+ if (status & 0x240)
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+ break;
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+ mdelay(1);
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}
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WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x80001);
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