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@@ -3810,6 +3810,17 @@ static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
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return rpn;
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return rpn;
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}
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}
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+static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
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+{
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+ u32 val, rp1;
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+
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+ val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
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+
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+ rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
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+
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+ return rp1;
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+}
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+
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static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
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static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
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{
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{
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u32 val, rp0;
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u32 val, rp0;
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@@ -3952,6 +3963,11 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
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vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
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vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
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dev_priv->rps.efficient_freq);
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dev_priv->rps.efficient_freq);
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+ dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
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+ DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
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+ vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
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+ dev_priv->rps.rp1_freq);
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+
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dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
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dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
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DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
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DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
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vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
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