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@@ -163,7 +163,6 @@ static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
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struct phy_device *phy)
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{
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struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
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- s8 cpu_port = ds->dst->cpu_dp->index;
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unsigned int i;
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u32 reg;
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@@ -184,9 +183,6 @@ static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
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reg |= i << (PRT_TO_QID_SHIFT * i);
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core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
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- /* Clear the Rx and Tx disable bits and set to no spanning tree */
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- core_writel(priv, 0, CORE_G_PCTL_PORT(port));
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-
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/* Re-enable the GPHY and re-apply workarounds */
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if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
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bcm_sf2_gphy_enable_set(ds, true);
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@@ -209,23 +205,7 @@ static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
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if (port == priv->moca_port)
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bcm_sf2_port_intr_enable(priv, port);
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- /* Set this port, and only this one to be in the default VLAN,
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- * if member of a bridge, restore its membership prior to
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- * bringing down this port.
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- */
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- reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
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- reg &= ~PORT_VLAN_CTRL_MASK;
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- reg |= (1 << port);
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- reg |= priv->dev->ports[port].vlan_ctl_mask;
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- core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
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-
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- b53_imp_vlan_setup(ds, cpu_port);
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-
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- /* If EEE was enabled, restore it */
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- if (priv->dev->ports[port].eee.eee_enabled)
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- b53_eee_enable_set(ds, port, true);
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-
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- return 0;
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+ return b53_enable_port(ds, port, phy);
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}
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static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
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@@ -248,9 +228,7 @@ static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
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else
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off = CORE_G_PCTL_PORT(port);
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- reg = core_readl(priv, off);
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- reg |= RX_DIS | TX_DIS;
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- core_writel(priv, reg, off);
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+ b53_disable_port(ds, port, phy);
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/* Power down the port memory */
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reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
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