drm/nouveau/sw: namespace + nvidia gpu names (no binary change)

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/include/nvkm/core/os.h

@@ -251,5 +251,7 @@
 #define nouveau_fifo_chan nvkm_fifo_chan
 #define nouveau_fifo nvkm_fifo
 #define nouveau_gr nvkm_gr
+#define nouveau_sw nvkm_sw
+#define nouveau_sw_chan nvkm_sw_chan
 
 #endif

drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h

@@ -1,51 +1,50 @@
-#ifndef __NOUVEAU_SW_H__
-#define __NOUVEAU_SW_H__
-
-#include <core/engine.h>
+#ifndef __NVKM_SW_H__
+#define __NVKM_SW_H__
 #include <core/engctx.h>
 
-struct nouveau_sw_chan {
-	struct nouveau_engctx base;
+struct nvkm_sw_chan {
+	struct nvkm_engctx base;
 
 	int (*flip)(void *);
 	void *flip_data;
 };
 
-#define nouveau_sw_context_create(p,e,c,d)                               \
-	nouveau_engctx_create((p), (e), (c), (p), 0, 0, 0, (d))
-#define nouveau_sw_context_destroy(d)                                    \
-	nouveau_engctx_destroy(&(d)->base)
-#define nouveau_sw_context_init(d)                                       \
-	nouveau_engctx_init(&(d)->base)
-#define nouveau_sw_context_fini(d,s)                                     \
-	nouveau_engctx_fini(&(d)->base, (s))
-
-#define _nouveau_sw_context_dtor _nouveau_engctx_dtor
-#define _nouveau_sw_context_init _nouveau_engctx_init
-#define _nouveau_sw_context_fini _nouveau_engctx_fini
-
-struct nouveau_sw {
-	struct nouveau_engine base;
-};
-
-#define nouveau_sw_create(p,e,c,d)                                       \
-	nouveau_engine_create((p), (e), (c), true, "SW", "software", (d))
-#define nouveau_sw_destroy(d)                                            \
-	nouveau_engine_destroy(&(d)->base)
-#define nouveau_sw_init(d)                                               \
-	nouveau_engine_init(&(d)->base)
-#define nouveau_sw_fini(d,s)                                             \
-	nouveau_engine_fini(&(d)->base, (s))
+#define nvkm_sw_context_create(p,e,c,d)                               \
+	nvkm_engctx_create((p), (e), (c), (p), 0, 0, 0, (d))
+#define nvkm_sw_context_destroy(d)                                    \
+	nvkm_engctx_destroy(&(d)->base)
+#define nvkm_sw_context_init(d)                                       \
+	nvkm_engctx_init(&(d)->base)
+#define nvkm_sw_context_fini(d,s)                                     \
+	nvkm_engctx_fini(&(d)->base, (s))
 
-#define _nouveau_sw_dtor _nouveau_engine_dtor
-#define _nouveau_sw_init _nouveau_engine_init
-#define _nouveau_sw_fini _nouveau_engine_fini
+#define _nvkm_sw_context_dtor _nvkm_engctx_dtor
+#define _nvkm_sw_context_init _nvkm_engctx_init
+#define _nvkm_sw_context_fini _nvkm_engctx_fini
 
-extern struct nouveau_oclass *nv04_sw_oclass;
-extern struct nouveau_oclass *nv10_sw_oclass;
-extern struct nouveau_oclass *nv50_sw_oclass;
-extern struct nouveau_oclass *nvc0_sw_oclass;
+#include <core/engine.h>
 
-void nv04_sw_intr(struct nouveau_subdev *);
+struct nvkm_sw {
+	struct nvkm_engine base;
+};
 
+#define nvkm_sw_create(p,e,c,d)                                       \
+	nvkm_engine_create((p), (e), (c), true, "SW", "software", (d))
+#define nvkm_sw_destroy(d)                                            \
+	nvkm_engine_destroy(&(d)->base)
+#define nvkm_sw_init(d)                                               \
+	nvkm_engine_init(&(d)->base)
+#define nvkm_sw_fini(d,s)                                             \
+	nvkm_engine_fini(&(d)->base, (s))
+
+#define _nvkm_sw_dtor _nvkm_engine_dtor
+#define _nvkm_sw_init _nvkm_engine_init
+#define _nvkm_sw_fini _nvkm_engine_fini
+
+extern struct nvkm_oclass *nv04_sw_oclass;
+extern struct nvkm_oclass *nv10_sw_oclass;
+extern struct nvkm_oclass *nv50_sw_oclass;
+extern struct nvkm_oclass *gf100_sw_oclass;
+
+void nv04_sw_intr(struct nvkm_subdev *);
 #endif

drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c

@@ -85,7 +85,7 @@ gm100_identify(struct nouveau_device *device)
 #endif
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gm107_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
@@ -129,7 +129,7 @@ gm100_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
 #if 0
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_gr_oclass;
 #endif
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gm204_disp_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c

@@ -82,7 +82,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf100_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gf100_msvld_oclass;
@@ -115,7 +115,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gf100_msvld_oclass;
@@ -148,7 +148,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gf100_msvld_oclass;
@@ -180,7 +180,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gf100_msvld_oclass;
@@ -213,7 +213,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gf100_msvld_oclass;
@@ -245,7 +245,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf108_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gf100_msvld_oclass;
@@ -277,7 +277,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf110_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gf100_msvld_oclass;
@@ -310,7 +310,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf119_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gf100_msvld_oclass;
@@ -340,7 +340,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf117_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gf100_msvld_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c

@@ -82,7 +82,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gk104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gk104_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
@@ -116,7 +116,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gk104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gk104_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
@@ -150,7 +150,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gk104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gk104_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
@@ -176,7 +176,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_BAR    ] = &gk20a_bar_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk20a_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gk20a_gr_oclass;
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &gk104_pm_oclass;
@@ -206,7 +206,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gk110_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gk110_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
@@ -240,7 +240,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gk110b_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gk110_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
@@ -274,7 +274,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gk208_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gk110_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
@@ -307,7 +307,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;
-		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
+		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gk208_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gk110_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild

@@ -1,4 +1,4 @@
 nvkm-y += nvkm/engine/sw/nv04.o
 nvkm-y += nvkm/engine/sw/nv10.o
 nvkm-y += nvkm/engine/sw/nv50.o
-nvkm-y += nvkm/engine/sw/nvc0.o
+nvkm-y += nvkm/engine/sw/gf100.o

drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c → drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c

@@ -21,25 +21,17 @@
  *
  * Authors: Ben Skeggs
  */
-
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/event.h>
+#include "nv50.h"
 
 #include <subdev/bar.h>
 
-#include <engine/sw.h>
-#include <engine/disp.h>
-
-#include "nv50.h"
-
 /*******************************************************************************
  * software object classes
  ******************************************************************************/
 
 static int
-nvc0_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
-				 void *args, u32 size)
+gf100_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd,
+			    void *args, u32 size)
 {
 	struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
 	u64 data = *(u32 *)args;
@@ -54,8 +46,8 @@ nvc0_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
 }
 
 static int
-nvc0_sw_mthd_mp_control(struct nouveau_object *object, u32 mthd,
-                              void *args, u32 size)
+gf100_sw_mthd_mp_control(struct nvkm_object *object, u32 mthd,
+			 void *args, u32 size)
 {
 	struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
 	struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
@@ -79,22 +71,22 @@ nvc0_sw_mthd_mp_control(struct nouveau_object *object, u32 mthd,
 	return 0;
 }
 
-static struct nouveau_omthds
-nvc0_sw_omthds[] = {
-	{ 0x0400, 0x0400, nvc0_sw_mthd_vblsem_offset },
-	{ 0x0404, 0x0404, nvc0_sw_mthd_vblsem_offset },
+static struct nvkm_omthds
+gf100_sw_omthds[] = {
+	{ 0x0400, 0x0400, gf100_sw_mthd_vblsem_offset },
+	{ 0x0404, 0x0404, gf100_sw_mthd_vblsem_offset },
 	{ 0x0408, 0x0408, nv50_sw_mthd_vblsem_value },
 	{ 0x040c, 0x040c, nv50_sw_mthd_vblsem_release },
 	{ 0x0500, 0x0500, nv50_sw_mthd_flip },
-	{ 0x0600, 0x0600, nvc0_sw_mthd_mp_control },
-	{ 0x0644, 0x0644, nvc0_sw_mthd_mp_control },
-	{ 0x06ac, 0x06ac, nvc0_sw_mthd_mp_control },
+	{ 0x0600, 0x0600, gf100_sw_mthd_mp_control },
+	{ 0x0644, 0x0644, gf100_sw_mthd_mp_control },
+	{ 0x06ac, 0x06ac, gf100_sw_mthd_mp_control },
 	{}
 };
 
-static struct nouveau_oclass
-nvc0_sw_sclass[] = {
-	{ 0x906e, &nouveau_object_ofuncs, nvc0_sw_omthds },
+static struct nvkm_oclass
+gf100_sw_sclass[] = {
+	{ 0x906e, &nvkm_object_ofuncs, gf100_sw_omthds },
 	{}
 };
 
@@ -103,12 +95,12 @@ nvc0_sw_sclass[] = {
  ******************************************************************************/
 
 static int
-nvc0_sw_vblsem_release(struct nvkm_notify *notify)
+gf100_sw_vblsem_release(struct nvkm_notify *notify)
 {
 	struct nv50_sw_chan *chan =
 		container_of(notify, typeof(*chan), vblank.notify[notify->index]);
 	struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
-	struct nouveau_bar *bar = nouveau_bar(priv);
+	struct nvkm_bar *bar = nvkm_bar(priv);
 
 	nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
 	bar->flush(bar);
@@ -120,30 +112,30 @@ nvc0_sw_vblsem_release(struct nvkm_notify *notify)
 }
 
 static struct nv50_sw_cclass
-nvc0_sw_cclass = {
+gf100_sw_cclass = {
 	.base.handle = NV_ENGCTX(SW, 0xc0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
+	.base.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = nv50_sw_context_ctor,
 		.dtor = nv50_sw_context_dtor,
-		.init = _nouveau_sw_context_init,
-		.fini = _nouveau_sw_context_fini,
+		.init = _nvkm_sw_context_init,
+		.fini = _nvkm_sw_context_fini,
 	},
-	.vblank = nvc0_sw_vblsem_release,
+	.vblank = gf100_sw_vblsem_release,
 };
 
 /*******************************************************************************
  * software engine/subdev functions
  ******************************************************************************/
 
-struct nouveau_oclass *
-nvc0_sw_oclass = &(struct nv50_sw_oclass) {
+struct nvkm_oclass *
+gf100_sw_oclass = &(struct nv50_sw_oclass) {
 	.base.handle = NV_ENGINE(SW, 0xc0),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
+	.base.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = nv50_sw_ctor,
-		.dtor = _nouveau_sw_dtor,
-		.init = _nouveau_sw_init,
-		.fini = _nouveau_sw_fini,
+		.dtor = _nvkm_sw_dtor,
+		.init = _nvkm_sw_init,
+		.fini = _nvkm_sw_fini,
 	},
-	.cclass = &nvc0_sw_cclass.base,
-	.sclass =  nvc0_sw_sclass,
+	.cclass = &gf100_sw_cclass.base,
+	.sclass =  gf100_sw_sclass,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c

@@ -21,19 +21,15 @@
  *
  * Authors: Ben Skeggs
  */
-
-#include <core/os.h>
-#include <core/engctx.h>
-
 #include <engine/sw.h>
 #include <engine/fifo.h>
 
 struct nv04_sw_priv {
-	struct nouveau_sw base;
+	struct nvkm_sw base;
 };
 
 struct nv04_sw_chan {
-	struct nouveau_sw_chan base;
+	struct nvkm_sw_chan base;
 };
 
 /*******************************************************************************
@@ -41,18 +37,16 @@ struct nv04_sw_chan {
  ******************************************************************************/
 
 static int
-nv04_sw_set_ref(struct nouveau_object *object, u32 mthd,
-		      void *data, u32 size)
+nv04_sw_set_ref(struct nvkm_object *object, u32 mthd, void *data, u32 size)
 {
-	struct nouveau_object *channel = (void *)nv_engctx(object->parent);
-	struct nouveau_fifo_chan *fifo = (void *)channel->parent;
+	struct nvkm_object *channel = (void *)nv_engctx(object->parent);
+	struct nvkm_fifo_chan *fifo = (void *)channel->parent;
 	atomic_set(&fifo->refcnt, *(u32*)data);
 	return 0;
 }
 
 static int
-nv04_sw_flip(struct nouveau_object *object, u32 mthd,
-		   void *args, u32 size)
+nv04_sw_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size)
 {
 	struct nv04_sw_chan *chan = (void *)nv_engctx(object->parent);
 	if (chan->base.flip)
@@ -60,16 +54,16 @@ nv04_sw_flip(struct nouveau_object *object, u32 mthd,
 	return -EINVAL;
 }
 
-static struct nouveau_omthds
+static struct nvkm_omthds
 nv04_sw_omthds[] = {
 	{ 0x0150, 0x0150, nv04_sw_set_ref },
 	{ 0x0500, 0x0500, nv04_sw_flip },
 	{}
 };
 
-static struct nouveau_oclass
+static struct nvkm_oclass
 nv04_sw_sclass[] = {
-	{ 0x006e, &nouveau_object_ofuncs, nv04_sw_omthds },
+	{ 0x006e, &nvkm_object_ofuncs, nv04_sw_omthds },
 	{}
 };
 
@@ -78,15 +72,14 @@ nv04_sw_sclass[] = {
  ******************************************************************************/
 
 static int
-nv04_sw_context_ctor(struct nouveau_object *parent,
-		      struct nouveau_object *engine,
-		      struct nouveau_oclass *oclass, void *data, u32 size,
-		      struct nouveau_object **pobject)
+nv04_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+		     struct nvkm_oclass *oclass, void *data, u32 size,
+		     struct nvkm_object **pobject)
 {
 	struct nv04_sw_chan *chan;
 	int ret;
 
-	ret = nouveau_sw_context_create(parent, engine, oclass, &chan);
+	ret = nvkm_sw_context_create(parent, engine, oclass, &chan);
 	*pobject = nv_object(chan);
 	if (ret)
 		return ret;
@@ -94,14 +87,14 @@ nv04_sw_context_ctor(struct nouveau_object *parent,
 	return 0;
 }
 
-static struct nouveau_oclass
+static struct nvkm_oclass
 nv04_sw_cclass = {
 	.handle = NV_ENGCTX(SW, 0x04),
-	.ofuncs = &(struct nouveau_ofuncs) {
+	.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = nv04_sw_context_ctor,
-		.dtor = _nouveau_sw_context_dtor,
-		.init = _nouveau_sw_context_init,
-		.fini = _nouveau_sw_context_fini,
+		.dtor = _nvkm_sw_context_dtor,
+		.init = _nvkm_sw_context_init,
+		.fini = _nvkm_sw_context_fini,
 	},
 };
 
@@ -110,20 +103,20 @@ nv04_sw_cclass = {
  ******************************************************************************/
 
 void
-nv04_sw_intr(struct nouveau_subdev *subdev)
+nv04_sw_intr(struct nvkm_subdev *subdev)
 {
 	nv_mask(subdev, 0x000100, 0x80000000, 0x00000000);
 }
 
 static int
-nv04_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
+nv04_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+	     struct nvkm_oclass *oclass, void *data, u32 size,
+	     struct nvkm_object **pobject)
 {
 	struct nv04_sw_priv *priv;
 	int ret;
 
-	ret = nouveau_sw_create(parent, engine, oclass, &priv);
+	ret = nvkm_sw_create(parent, engine, oclass, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -134,13 +127,13 @@ nv04_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	return 0;
 }
 
-struct nouveau_oclass *
-nv04_sw_oclass = &(struct nouveau_oclass) {
+struct nvkm_oclass *
+nv04_sw_oclass = &(struct nvkm_oclass) {
 	.handle = NV_ENGINE(SW, 0x04),
-	.ofuncs = &(struct nouveau_ofuncs) {
+	.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = nv04_sw_ctor,
-		.dtor = _nouveau_sw_dtor,
-		.init = _nouveau_sw_init,
-		.fini = _nouveau_sw_fini,
+		.dtor = _nvkm_sw_dtor,
+		.init = _nvkm_sw_init,
+		.fini = _nvkm_sw_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c

@@ -21,18 +21,14 @@
  *
  * Authors: Ben Skeggs
  */
-
-#include <core/os.h>
-#include <core/engctx.h>
-
 #include <engine/sw.h>
 
 struct nv10_sw_priv {
-	struct nouveau_sw base;
+	struct nvkm_sw base;
 };
 
 struct nv10_sw_chan {
-	struct nouveau_sw_chan base;
+	struct nvkm_sw_chan base;
 };
 
 /*******************************************************************************
@@ -40,8 +36,7 @@ struct nv10_sw_chan {
  ******************************************************************************/
 
 static int
-nv10_sw_flip(struct nouveau_object *object, u32 mthd,
-		   void *args, u32 size)
+nv10_sw_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size)
 {
 	struct nv10_sw_chan *chan = (void *)nv_engctx(object->parent);
 	if (chan->base.flip)
@@ -49,15 +44,15 @@ nv10_sw_flip(struct nouveau_object *object, u32 mthd,
 	return -EINVAL;
 }
 
-static struct nouveau_omthds
+static struct nvkm_omthds
 nv10_sw_omthds[] = {
 	{ 0x0500, 0x0500, nv10_sw_flip },
 	{}
 };
 
-static struct nouveau_oclass
+static struct nvkm_oclass
 nv10_sw_sclass[] = {
-	{ 0x016e, &nouveau_object_ofuncs, nv10_sw_omthds },
+	{ 0x016e, &nvkm_object_ofuncs, nv10_sw_omthds },
 	{}
 };
 
@@ -66,15 +61,14 @@ nv10_sw_sclass[] = {
  ******************************************************************************/
 
 static int
-nv10_sw_context_ctor(struct nouveau_object *parent,
-		      struct nouveau_object *engine,
-		      struct nouveau_oclass *oclass, void *data, u32 size,
-		      struct nouveau_object **pobject)
+nv10_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+		     struct nvkm_oclass *oclass, void *data, u32 size,
+		     struct nvkm_object **pobject)
 {
 	struct nv10_sw_chan *chan;
 	int ret;
 
-	ret = nouveau_sw_context_create(parent, engine, oclass, &chan);
+	ret = nvkm_sw_context_create(parent, engine, oclass, &chan);
 	*pobject = nv_object(chan);
 	if (ret)
 		return ret;
@@ -82,14 +76,14 @@ nv10_sw_context_ctor(struct nouveau_object *parent,
 	return 0;
 }
 
-static struct nouveau_oclass
+static struct nvkm_oclass
 nv10_sw_cclass = {
 	.handle = NV_ENGCTX(SW, 0x04),
-	.ofuncs = &(struct nouveau_ofuncs) {
+	.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = nv10_sw_context_ctor,
-		.dtor = _nouveau_sw_context_dtor,
-		.init = _nouveau_sw_context_init,
-		.fini = _nouveau_sw_context_fini,
+		.dtor = _nvkm_sw_context_dtor,
+		.init = _nvkm_sw_context_init,
+		.fini = _nvkm_sw_context_fini,
 	},
 };
 
@@ -98,14 +92,14 @@ nv10_sw_cclass = {
  ******************************************************************************/
 
 static int
-nv10_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
+nv10_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+	     struct nvkm_oclass *oclass, void *data, u32 size,
+	     struct nvkm_object **pobject)
 {
 	struct nv10_sw_priv *priv;
 	int ret;
 
-	ret = nouveau_sw_create(parent, engine, oclass, &priv);
+	ret = nvkm_sw_create(parent, engine, oclass, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -116,13 +110,13 @@ nv10_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	return 0;
 }
 
-struct nouveau_oclass *
-nv10_sw_oclass = &(struct nouveau_oclass) {
+struct nvkm_oclass *
+nv10_sw_oclass = &(struct nvkm_oclass) {
 	.handle = NV_ENGINE(SW, 0x10),
-	.ofuncs = &(struct nouveau_ofuncs) {
+	.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = nv10_sw_ctor,
-		.dtor = _nouveau_sw_dtor,
-		.init = _nouveau_sw_init,
-		.fini = _nouveau_sw_fini,
+		.dtor = _nvkm_sw_dtor,
+		.init = _nvkm_sw_init,
+		.fini = _nvkm_sw_fini,
 	},
 };

drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c

@@ -21,51 +21,45 @@
  *
  * Authors: Ben Skeggs
  */
+#include "nv50.h"
 
-#include <core/os.h>
 #include <core/device.h>
-#include <core/engctx.h>
-#include <core/namedb.h>
 #include <core/handle.h>
-#include <core/gpuobj.h>
-#include <core/event.h>
-#include <nvif/event.h>
-
-#include <subdev/bar.h>
-
+#include <core/namedb.h>
 #include <engine/disp.h>
+#include <subdev/bar.h>
 
-#include "nv50.h"
+#include <nvif/event.h>
 
 /*******************************************************************************
  * software object classes
  ******************************************************************************/
 
 static int
-nv50_sw_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd,
-			      void *args, u32 size)
+nv50_sw_mthd_dma_vblsem(struct nvkm_object *object, u32 mthd,
+			void *args, u32 size)
 {
 	struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
-	struct nouveau_fifo_chan *fifo = (void *)nv_object(chan)->parent;
-	struct nouveau_handle *handle;
+	struct nvkm_fifo_chan *fifo = (void *)nv_object(chan)->parent;
+	struct nvkm_handle *handle;
 	int ret = -EINVAL;
 
-	handle = nouveau_namedb_get(nv_namedb(fifo), *(u32 *)args);
+	handle = nvkm_namedb_get(nv_namedb(fifo), *(u32 *)args);
 	if (!handle)
 		return -ENOENT;
 
 	if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) {
-		struct nouveau_gpuobj *gpuobj = nv_gpuobj(handle->object);
+		struct nvkm_gpuobj *gpuobj = nv_gpuobj(handle->object);
 		chan->vblank.ctxdma = gpuobj->node->offset >> 4;
 		ret = 0;
 	}
-	nouveau_namedb_put(handle);
+	nvkm_namedb_put(handle);
 	return ret;
 }
 
 static int
-nv50_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
-				 void *args, u32 size)
+nv50_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd,
+			   void *args, u32 size)
 {
 	struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
 	chan->vblank.offset = *(u32 *)args;
@@ -73,8 +67,8 @@ nv50_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
 }
 
 int
-nv50_sw_mthd_vblsem_value(struct nouveau_object *object, u32 mthd,
-				void *args, u32 size)
+nv50_sw_mthd_vblsem_value(struct nvkm_object *object, u32 mthd,
+			  void *args, u32 size)
 {
 	struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
 	chan->vblank.value = *(u32 *)args;
@@ -82,12 +76,12 @@ nv50_sw_mthd_vblsem_value(struct nouveau_object *object, u32 mthd,
 }
 
 int
-nv50_sw_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
-				  void *args, u32 size)
+nv50_sw_mthd_vblsem_release(struct nvkm_object *object, u32 mthd,
+			    void *args, u32 size)
 {
 	struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
 	u32 head = *(u32 *)args;
-	if (head >= nouveau_disp(chan)->vblank.index_nr)
+	if (head >= nvkm_disp(chan)->vblank.index_nr)
 		return -EINVAL;
 
 	nvkm_notify_get(&chan->vblank.notify[head]);
@@ -95,8 +89,7 @@ nv50_sw_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
 }
 
 int
-nv50_sw_mthd_flip(struct nouveau_object *object, u32 mthd,
-			void *args, u32 size)
+nv50_sw_mthd_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size)
 {
 	struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
 	if (chan->base.flip)
@@ -104,7 +97,7 @@ nv50_sw_mthd_flip(struct nouveau_object *object, u32 mthd,
 	return -EINVAL;
 }
 
-static struct nouveau_omthds
+static struct nvkm_omthds
 nv50_sw_omthds[] = {
 	{ 0x018c, 0x018c, nv50_sw_mthd_dma_vblsem },
 	{ 0x0400, 0x0400, nv50_sw_mthd_vblsem_offset },
@@ -114,9 +107,9 @@ nv50_sw_omthds[] = {
 	{}
 };
 
-static struct nouveau_oclass
+static struct nvkm_oclass
 nv50_sw_sclass[] = {
-	{ 0x506e, &nouveau_object_ofuncs, nv50_sw_omthds },
+	{ 0x506e, &nvkm_object_ofuncs, nv50_sw_omthds },
 	{}
 };
 
@@ -130,7 +123,7 @@ nv50_sw_vblsem_release(struct nvkm_notify *notify)
 	struct nv50_sw_chan *chan =
 		container_of(notify, typeof(*chan), vblank.notify[notify->index]);
 	struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
-	struct nouveau_bar *bar = nouveau_bar(priv);
+	struct nvkm_bar *bar = nvkm_bar(priv);
 
 	nv_wr32(priv, 0x001704, chan->vblank.channel);
 	nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
@@ -148,7 +141,7 @@ nv50_sw_vblsem_release(struct nvkm_notify *notify)
 }
 
 void
-nv50_sw_context_dtor(struct nouveau_object *object)
+nv50_sw_context_dtor(struct nvkm_object *object)
 {
 	struct nv50_sw_chan *chan = (void *)object;
 	int i;
@@ -156,21 +149,20 @@ nv50_sw_context_dtor(struct nouveau_object *object)
 	for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++)
 		nvkm_notify_fini(&chan->vblank.notify[i]);
 
-	nouveau_sw_context_destroy(&chan->base);
+	nvkm_sw_context_destroy(&chan->base);
 }
 
 int
-nv50_sw_context_ctor(struct nouveau_object *parent,
-			   struct nouveau_object *engine,
-			   struct nouveau_oclass *oclass, void *data, u32 size,
-			   struct nouveau_object **pobject)
+nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+		     struct nvkm_oclass *oclass, void *data, u32 size,
+		     struct nvkm_object **pobject)
 {
-	struct nouveau_disp *pdisp = nouveau_disp(parent);
+	struct nvkm_disp *pdisp = nvkm_disp(parent);
 	struct nv50_sw_cclass *pclass = (void *)oclass;
 	struct nv50_sw_chan *chan;
 	int ret, i;
 
-	ret = nouveau_sw_context_create(parent, engine, oclass, &chan);
+	ret = nvkm_sw_context_create(parent, engine, oclass, &chan);
 	*pobject = nv_object(chan);
 	if (ret)
 		return ret;
@@ -195,11 +187,11 @@ nv50_sw_context_ctor(struct nouveau_object *parent,
 static struct nv50_sw_cclass
 nv50_sw_cclass = {
 	.base.handle = NV_ENGCTX(SW, 0x50),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
+	.base.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = nv50_sw_context_ctor,
 		.dtor = nv50_sw_context_dtor,
-		.init = _nouveau_sw_context_init,
-		.fini = _nouveau_sw_context_fini,
+		.init = _nvkm_sw_context_init,
+		.fini = _nvkm_sw_context_fini,
 	},
 	.vblank = nv50_sw_vblsem_release,
 };
@@ -209,15 +201,15 @@ nv50_sw_cclass = {
  ******************************************************************************/
 
 int
-nv50_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-		   struct nouveau_oclass *oclass, void *data, u32 size,
-		   struct nouveau_object **pobject)
+nv50_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+	     struct nvkm_oclass *oclass, void *data, u32 size,
+	     struct nvkm_object **pobject)
 {
 	struct nv50_sw_oclass *pclass = (void *)oclass;
 	struct nv50_sw_priv *priv;
 	int ret;
 
-	ret = nouveau_sw_create(parent, engine, oclass, &priv);
+	ret = nvkm_sw_create(parent, engine, oclass, &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -228,14 +220,14 @@ nv50_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	return 0;
 }
 
-struct nouveau_oclass *
+struct nvkm_oclass *
 nv50_sw_oclass = &(struct nv50_sw_oclass) {
 	.base.handle = NV_ENGINE(SW, 0x50),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
+	.base.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = nv50_sw_ctor,
-		.dtor = _nouveau_sw_dtor,
-		.init = _nouveau_sw_init,
-		.fini = _nouveau_sw_fini,
+		.dtor = _nvkm_sw_dtor,
+		.init = _nvkm_sw_init,
+		.fini = _nvkm_sw_fini,
 	},
 	.cclass = &nv50_sw_cclass.base,
 	.sclass =  nv50_sw_sclass,

drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h

@@ -4,26 +4,26 @@
 #include <core/notify.h>
 
 struct nv50_sw_oclass {
-	struct nouveau_oclass base;
-	struct nouveau_oclass *cclass;
-	struct nouveau_oclass *sclass;
+	struct nvkm_oclass base;
+	struct nvkm_oclass *cclass;
+	struct nvkm_oclass *sclass;
 };
 
 struct nv50_sw_priv {
-	struct nouveau_sw base;
+	struct nvkm_sw base;
 };
 
-int  nv50_sw_ctor(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void *, u32,
-			struct nouveau_object **);
+int  nv50_sw_ctor(struct nvkm_object *, struct nvkm_object *,
+			struct nvkm_oclass *, void *, u32,
+			struct nvkm_object **);
 
 struct nv50_sw_cclass {
-	struct nouveau_oclass base;
+	struct nvkm_oclass base;
 	int (*vblank)(struct nvkm_notify *);
 };
 
 struct nv50_sw_chan {
-	struct nouveau_sw_chan base;
+	struct nvkm_sw_chan base;
 	struct {
 		struct nvkm_notify notify[4];
 		u32 channel;
@@ -33,14 +33,13 @@ struct nv50_sw_chan {
 	} vblank;
 };
 
-int  nv50_sw_context_ctor(struct nouveau_object *,
-				struct nouveau_object *,
-				struct nouveau_oclass *, void *, u32,
-				struct nouveau_object **);
-void nv50_sw_context_dtor(struct nouveau_object *);
-
-int nv50_sw_mthd_vblsem_value(struct nouveau_object *, u32, void *, u32);
-int nv50_sw_mthd_vblsem_release(struct nouveau_object *, u32, void *, u32);
-int nv50_sw_mthd_flip(struct nouveau_object *, u32, void *, u32);
+int  nv50_sw_context_ctor(struct nvkm_object *,
+				struct nvkm_object *,
+				struct nvkm_oclass *, void *, u32,
+				struct nvkm_object **);
+void nv50_sw_context_dtor(struct nvkm_object *);
 
+int nv50_sw_mthd_vblsem_value(struct nvkm_object *, u32, void *, u32);
+int nv50_sw_mthd_vblsem_release(struct nvkm_object *, u32, void *, u32);
+int nv50_sw_mthd_flip(struct nvkm_object *, u32, void *, u32);
 #endif