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@@ -229,7 +229,26 @@
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#define CLK_SDIO1_2X_EN 65
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#define CLK_SDIO2_2X_EN 66
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#define CLK_EMMC_2X_EN 67
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-#define CLK_AON_GATE_NUM (CLK_EMMC_2X_EN + 1)
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+#define CLK_ARCH_RTC_EB 68
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+#define CLK_KPB_RTC_EB 69
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+#define CLK_AON_SYST_RTC_EB 70
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+#define CLK_AP_SYST_RTC_EB 71
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+#define CLK_AON_TMR_RTC_EB 72
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+#define CLK_AP_TMR0_RTC_EB 73
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+#define CLK_EIC_RTC_EB 74
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+#define CLK_EIC_RTCDV5_EB 75
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+#define CLK_AP_WDG_RTC_EB 76
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+#define CLK_AP_TMR1_RTC_EB 77
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+#define CLK_AP_TMR2_RTC_EB 78
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+#define CLK_DCXO_TMR_RTC_EB 79
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+#define CLK_BB_CAL_RTC_EB 80
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+#define CLK_AVS_BIG_RTC_EB 81
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+#define CLK_AVS_LIT_RTC_EB 82
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+#define CLK_AVS_GPU0_RTC_EB 83
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+#define CLK_AVS_GPU1_RTC_EB 84
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+#define CLK_GPU_TS_EB 85
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+#define CLK_RTCDV10_EB 86
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+#define CLK_AON_GATE_NUM (CLK_RTCDV10_EB + 1)
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#define CLK_LIT_MCU 0
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#define CLK_BIG_MCU 1
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