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@@ -37,6 +37,10 @@
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#ifndef __DWC2_CORE_H__
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#define __DWC2_CORE_H__
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+#include <linux/phy/phy.h>
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+#include <linux/regulator/consumer.h>
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+#include <linux/usb/gadget.h>
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+#include <linux/usb/otg.h>
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#include <linux/usb/phy.h>
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#include "hw.h"
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@@ -54,6 +58,184 @@ static inline void do_write(u32 value, void *addr)
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/* Maximum number of Endpoints/HostChannels */
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#define MAX_EPS_CHANNELS 16
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+/* s3c-hsotg declarations */
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+static const char * const s3c_hsotg_supply_names[] = {
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+ "vusb_d", /* digital USB supply, 1.2V */
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+ "vusb_a", /* analog USB supply, 1.1V */
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+};
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+
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+/*
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+ * EP0_MPS_LIMIT
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+ *
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+ * Unfortunately there seems to be a limit of the amount of data that can
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+ * be transferred by IN transactions on EP0. This is either 127 bytes or 3
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+ * packets (which practically means 1 packet and 63 bytes of data) when the
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+ * MPS is set to 64.
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+ *
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+ * This means if we are wanting to move >127 bytes of data, we need to
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+ * split the transactions up, but just doing one packet at a time does
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+ * not work (this may be an implicit DATA0 PID on first packet of the
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+ * transaction) and doing 2 packets is outside the controller's limits.
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+ *
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+ * If we try to lower the MPS size for EP0, then no transfers work properly
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+ * for EP0, and the system will fail basic enumeration. As no cause for this
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+ * has currently been found, we cannot support any large IN transfers for
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+ * EP0.
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+ */
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+#define EP0_MPS_LIMIT 64
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+
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+struct s3c_hsotg;
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+struct s3c_hsotg_req;
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+
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+/**
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+ * struct s3c_hsotg_ep - driver endpoint definition.
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+ * @ep: The gadget layer representation of the endpoint.
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+ * @name: The driver generated name for the endpoint.
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+ * @queue: Queue of requests for this endpoint.
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+ * @parent: Reference back to the parent device structure.
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+ * @req: The current request that the endpoint is processing. This is
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+ * used to indicate an request has been loaded onto the endpoint
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+ * and has yet to be completed (maybe due to data move, or simply
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+ * awaiting an ack from the core all the data has been completed).
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+ * @debugfs: File entry for debugfs file for this endpoint.
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+ * @lock: State lock to protect contents of endpoint.
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+ * @dir_in: Set to true if this endpoint is of the IN direction, which
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+ * means that it is sending data to the Host.
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+ * @index: The index for the endpoint registers.
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+ * @mc: Multi Count - number of transactions per microframe
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+ * @interval - Interval for periodic endpoints
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+ * @name: The name array passed to the USB core.
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+ * @halted: Set if the endpoint has been halted.
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+ * @periodic: Set if this is a periodic ep, such as Interrupt
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+ * @isochronous: Set if this is a isochronous ep
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+ * @sent_zlp: Set if we've sent a zero-length packet.
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+ * @total_data: The total number of data bytes done.
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+ * @fifo_size: The size of the FIFO (for periodic IN endpoints)
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+ * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
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+ * @last_load: The offset of data for the last start of request.
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+ * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
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+ *
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+ * This is the driver's state for each registered enpoint, allowing it
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+ * to keep track of transactions that need doing. Each endpoint has a
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+ * lock to protect the state, to try and avoid using an overall lock
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+ * for the host controller as much as possible.
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+ *
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+ * For periodic IN endpoints, we have fifo_size and fifo_load to try
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+ * and keep track of the amount of data in the periodic FIFO for each
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+ * of these as we don't have a status register that tells us how much
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+ * is in each of them. (note, this may actually be useless information
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+ * as in shared-fifo mode periodic in acts like a single-frame packet
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+ * buffer than a fifo)
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+ */
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+struct s3c_hsotg_ep {
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+ struct usb_ep ep;
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+ struct list_head queue;
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+ struct s3c_hsotg *parent;
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+ struct s3c_hsotg_req *req;
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+ struct dentry *debugfs;
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+
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+ unsigned long total_data;
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+ unsigned int size_loaded;
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+ unsigned int last_load;
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+ unsigned int fifo_load;
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+ unsigned short fifo_size;
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+
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+ unsigned char dir_in;
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+ unsigned char index;
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+ unsigned char mc;
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+ unsigned char interval;
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+
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+ unsigned int halted:1;
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+ unsigned int periodic:1;
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+ unsigned int isochronous:1;
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+ unsigned int sent_zlp:1;
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+
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+ char name[10];
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+};
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+
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+/**
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+ * struct s3c_hsotg - driver state.
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+ * @dev: The parent device supplied to the probe function
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+ * @driver: USB gadget driver
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+ * @phy: The otg phy transceiver structure for phy control.
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+ * @uphy: The otg phy transceiver structure for old USB phy control.
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+ * @plat: The platform specific configuration data. This can be removed once
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+ * all SoCs support usb transceiver.
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+ * @regs: The memory area mapped for accessing registers.
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+ * @irq: The IRQ number we are using
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+ * @supplies: Definition of USB power supplies
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+ * @phyif: PHY interface width
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+ * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
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+ * @num_of_eps: Number of available EPs (excluding EP0)
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+ * @debug_root: root directrory for debugfs.
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+ * @debug_file: main status file for debugfs.
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+ * @debug_fifo: FIFO status file for debugfs.
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+ * @ep0_reply: Request used for ep0 reply.
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+ * @ep0_buff: Buffer for EP0 reply data, if needed.
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+ * @ctrl_buff: Buffer for EP0 control requests.
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+ * @ctrl_req: Request for EP0 control packets.
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+ * @setup: NAK management for EP0 SETUP
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+ * @last_rst: Time of last reset
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+ * @eps: The endpoints being supplied to the gadget framework
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+ */
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+struct s3c_hsotg {
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+ struct device *dev;
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+ struct usb_gadget_driver *driver;
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+ struct phy *phy;
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+ struct usb_phy *uphy;
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+ struct s3c_hsotg_plat *plat;
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+
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+ spinlock_t lock;
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+
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+ void __iomem *regs;
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+ int irq;
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+ struct clk *clk;
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+
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+ struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)];
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+
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+ u32 phyif;
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+ unsigned int dedicated_fifos:1;
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+ unsigned char num_of_eps;
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+
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+ struct dentry *debug_root;
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+ struct dentry *debug_file;
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+ struct dentry *debug_fifo;
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+
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+ struct usb_request *ep0_reply;
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+ struct usb_request *ctrl_req;
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+ u8 ep0_buff[8];
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+ u8 ctrl_buff[8];
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+
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+ struct usb_gadget gadget;
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+ unsigned int setup;
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+ unsigned long last_rst;
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+ struct s3c_hsotg_ep *eps;
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+};
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+
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+/**
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+ * struct s3c_hsotg_req - data transfer request
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+ * @req: The USB gadget request
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+ * @queue: The list of requests for the endpoint this is queued for.
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+ * @in_progress: Has already had size/packets written to core
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+ * @mapped: DMA buffer for this request has been mapped via dma_map_single().
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+ */
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+struct s3c_hsotg_req {
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+ struct usb_request req;
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+ struct list_head queue;
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+ unsigned char in_progress;
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+ unsigned char mapped;
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+};
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+
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+#define call_gadget(_hs, _entry) \
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+do { \
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+ if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
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+ (_hs)->driver && (_hs)->driver->_entry) { \
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+ spin_unlock(&_hs->lock); \
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+ (_hs)->driver->_entry(&(_hs)->gadget); \
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+ spin_lock(&_hs->lock); \
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+ } \
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+} while (0)
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+
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struct dwc2_hsotg;
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struct dwc2_host_chan;
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Dinh Nguyen