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+* Socionext NetSec Ethernet Controller IP
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+
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+Required properties:
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+- compatible: Should be "socionext,synquacer-netsec"
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+- reg: Address and length of the control register area, followed by the
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+ address and length of the EEPROM holding the MAC address and
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+ microengine firmware
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+- interrupts: Should contain ethernet controller interrupt
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+- clocks: phandle to the PHY reference clock
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+- clock-names: Should be "phy_ref_clk"
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+- phy-mode: See ethernet.txt file in the same directory
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+- phy-handle: See ethernet.txt in the same directory.
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+
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+- mdio device tree subnode: When the Netsec has a phy connected to its local
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+ mdio, there must be device tree subnode with the following
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+ required properties:
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+
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+ - #address-cells: Must be <1>.
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+ - #size-cells: Must be <0>.
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+
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+ For each phy on the mdio bus, there must be a node with the following
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+ fields:
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+ - compatible: Refer to phy.txt
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+ - reg: phy id used to communicate to phy.
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+
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+Optional properties: (See ethernet.txt file in the same directory)
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+- dma-coherent: Boolean property, must only be present if memory
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+ accesses performed by the device are cache coherent.
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+- local-mac-address: See ethernet.txt in the same directory.
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+- mac-address: See ethernet.txt in the same directory.
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+- max-speed: See ethernet.txt in the same directory.
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+- max-frame-size: See ethernet.txt in the same directory.
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+
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+Example:
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+ eth0: ethernet@522d0000 {
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+ compatible = "socionext,synquacer-netsec";
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+ reg = <0 0x522d0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>;
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+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&clk_netsec>;
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+ clock-names = "phy_ref_clk";
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+ phy-mode = "rgmii";
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+ max-speed = <1000>;
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+ max-frame-size = <9000>;
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+ phy-handle = <&phy1>;
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+
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+ mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ phy1: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ };
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+ };
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