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@@ -73,7 +73,6 @@
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#include <asm/setup.h>
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#include <asm/setup.h>
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#include <asm/uv/uv.h>
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#include <asm/uv/uv.h>
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#include <linux/mc146818rtc.h>
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#include <linux/mc146818rtc.h>
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-#include <asm/smpboot_hooks.h>
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#include <asm/i8259.h>
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#include <asm/i8259.h>
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#include <asm/realmode.h>
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#include <asm/realmode.h>
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#include <asm/misc.h>
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#include <asm/misc.h>
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@@ -104,6 +103,71 @@ EXPORT_PER_CPU_SYMBOL(cpu_info);
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atomic_t init_deasserted;
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atomic_t init_deasserted;
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+static inline void smpboot_clear_io_apic_irqs(void)
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+{
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+#ifdef CONFIG_X86_IO_APIC
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+ io_apic_irqs = 0;
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+#endif
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+}
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+
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+static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
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+{
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&rtc_lock, flags);
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+ CMOS_WRITE(0xa, 0xf);
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+ spin_unlock_irqrestore(&rtc_lock, flags);
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+ local_flush_tlb();
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+ pr_debug("1.\n");
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+ *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
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+ start_eip >> 4;
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+ pr_debug("2.\n");
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+ *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
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+ start_eip & 0xf;
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+ pr_debug("3.\n");
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+}
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+
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+static inline void smpboot_restore_warm_reset_vector(void)
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+{
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+ unsigned long flags;
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+
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+ /*
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+ * Install writable page 0 entry to set BIOS data area.
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+ */
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+ local_flush_tlb();
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+
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+ /*
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+ * Paranoid: Set warm reset code and vector here back
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+ * to default values.
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+ */
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+ spin_lock_irqsave(&rtc_lock, flags);
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+ CMOS_WRITE(0, 0xf);
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+ spin_unlock_irqrestore(&rtc_lock, flags);
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+
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+ *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
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+}
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+
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+static inline void __init smpboot_setup_io_apic(void)
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+{
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+#ifdef CONFIG_X86_IO_APIC
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+ /*
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+ * Here we can be sure that there is an IO-APIC in the system. Let's
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+ * go and set it up:
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+ */
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+ if (!skip_ioapic_setup && nr_ioapics)
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+ setup_IO_APIC();
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+ else
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+ nr_ioapics = 0;
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+#endif
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+}
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+
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+static inline void smpboot_clear_io_apic(void)
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+{
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+#ifdef CONFIG_X86_IO_APIC
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+ nr_ioapics = 0;
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+#endif
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+}
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+
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/*
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/*
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* Report back to the Boot Processor during boot time or to the caller processor
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* Report back to the Boot Processor during boot time or to the caller processor
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* during CPU online.
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* during CPU online.
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