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@@ -101,14 +101,7 @@
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/* ARM Cortex M3 core, ID 0x82a */
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#define BCM4329_CORE_ARM_BASE 0x18002000
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#define BCM4329_RAMSIZE 0x48000
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-
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/* bcm43143 */
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-/* SDIO device core */
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-#define BCM43143_CORE_BUS_BASE 0x18002000
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-/* internal memory core */
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-#define BCM43143_CORE_SOCRAM_BASE 0x18004000
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-/* ARM Cortex M3 core, ID 0x82a */
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-#define BCM43143_CORE_ARM_BASE 0x18003000
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#define BCM43143_RAMSIZE 0x70000
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#define CORE_SB(base, field) \
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@@ -164,13 +157,6 @@ struct brcmf_core_priv {
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struct brcmf_chip_priv *chip;
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};
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-/* ARM CR4 core specific control flag bits */
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-#define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
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-
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-/* D11 core specific control flag bits */
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-#define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
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-#define D11_BCMA_IOCTL_PHYRESET 0x0008
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-
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struct brcmf_chip_priv {
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struct brcmf_chip pub;
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const struct brcmf_buscore_ops *ops;
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