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@@ -1177,6 +1177,23 @@ static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
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WREG32(mmHDP_MEM_POWER_LS, data);
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WREG32(mmHDP_MEM_POWER_LS, data);
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}
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}
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+static void vi_update_drm_light_sleep(struct amdgpu_device *adev,
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+ bool enable)
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+{
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+ uint32_t temp, data;
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+
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+ temp = data = RREG32(0x157a);
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+
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+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
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+ data |= 1;
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+ else
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+ data &= ~1;
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+
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+ if (temp != data)
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+ WREG32(0x157a, data);
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+}
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+
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+
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static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
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static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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bool enable)
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{
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{
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@@ -1337,6 +1354,8 @@ static int vi_common_set_clockgating_state(void *handle,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE ? true : false);
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vi_update_hdp_light_sleep(adev,
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vi_update_hdp_light_sleep(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE ? true : false);
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+ vi_update_drm_light_sleep(adev,
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+ state == AMD_CG_STATE_GATE ? true : false);
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break;
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break;
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case CHIP_TONGA:
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case CHIP_TONGA:
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case CHIP_POLARIS10:
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case CHIP_POLARIS10:
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