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@@ -111,16 +111,59 @@ static const char * const mx28_lradc_irq_names[] = {
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struct mxs_lradc_of_config {
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struct mxs_lradc_of_config {
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const int irq_count;
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const int irq_count;
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const char * const *irq_name;
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const char * const *irq_name;
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+ const uint32_t *vref_mv;
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+};
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+
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+#define VREF_MV_BASE 1850
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+
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+static const uint32_t mx23_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
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+ VREF_MV_BASE, /* CH0 */
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+ VREF_MV_BASE, /* CH1 */
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+ VREF_MV_BASE, /* CH2 */
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+ VREF_MV_BASE, /* CH3 */
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+ VREF_MV_BASE, /* CH4 */
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+ VREF_MV_BASE, /* CH5 */
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+ VREF_MV_BASE * 2, /* CH6 VDDIO */
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+ VREF_MV_BASE * 4, /* CH7 VBATT */
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+ VREF_MV_BASE, /* CH8 Temp sense 0 */
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+ VREF_MV_BASE, /* CH9 Temp sense 1 */
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+ VREF_MV_BASE, /* CH10 */
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+ VREF_MV_BASE, /* CH11 */
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+ VREF_MV_BASE, /* CH12 USB_DP */
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+ VREF_MV_BASE, /* CH13 USB_DN */
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+ VREF_MV_BASE, /* CH14 VBG */
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+ VREF_MV_BASE * 4, /* CH15 VDD5V */
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+};
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+
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+static const uint32_t mx28_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
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+ VREF_MV_BASE, /* CH0 */
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+ VREF_MV_BASE, /* CH1 */
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+ VREF_MV_BASE, /* CH2 */
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+ VREF_MV_BASE, /* CH3 */
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+ VREF_MV_BASE, /* CH4 */
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+ VREF_MV_BASE, /* CH5 */
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+ VREF_MV_BASE, /* CH6 */
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+ VREF_MV_BASE * 4, /* CH7 VBATT */
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+ VREF_MV_BASE, /* CH8 Temp sense 0 */
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+ VREF_MV_BASE, /* CH9 Temp sense 1 */
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+ VREF_MV_BASE * 2, /* CH10 VDDIO */
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+ VREF_MV_BASE, /* CH11 VTH */
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+ VREF_MV_BASE * 2, /* CH12 VDDA */
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+ VREF_MV_BASE, /* CH13 VDDD */
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+ VREF_MV_BASE, /* CH14 VBG */
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+ VREF_MV_BASE * 4, /* CH15 VDD5V */
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};
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};
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static const struct mxs_lradc_of_config mxs_lradc_of_config[] = {
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static const struct mxs_lradc_of_config mxs_lradc_of_config[] = {
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[IMX23_LRADC] = {
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[IMX23_LRADC] = {
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.irq_count = ARRAY_SIZE(mx23_lradc_irq_names),
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.irq_count = ARRAY_SIZE(mx23_lradc_irq_names),
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.irq_name = mx23_lradc_irq_names,
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.irq_name = mx23_lradc_irq_names,
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+ .vref_mv = mx23_vref_mv,
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},
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},
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[IMX28_LRADC] = {
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[IMX28_LRADC] = {
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.irq_count = ARRAY_SIZE(mx28_lradc_irq_names),
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.irq_count = ARRAY_SIZE(mx28_lradc_irq_names),
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.irq_name = mx28_lradc_irq_names,
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.irq_name = mx28_lradc_irq_names,
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+ .vref_mv = mx28_vref_mv,
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},
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},
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};
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};
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@@ -155,6 +198,8 @@ struct mxs_lradc {
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struct completion completion;
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struct completion completion;
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+ const uint32_t *vref_mv;
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+
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/*
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/*
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* Touchscreen LRADC channels receives a private slot in the CTRL4
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* Touchscreen LRADC channels receives a private slot in the CTRL4
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* register, the slot #7. Therefore only 7 slots instead of 8 in the
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* register, the slot #7. Therefore only 7 slots instead of 8 in the
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@@ -836,6 +881,8 @@ static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
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const struct iio_chan_spec *chan,
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const struct iio_chan_spec *chan,
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int *val, int *val2, long m)
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int *val, int *val2, long m)
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{
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{
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+ struct mxs_lradc *lradc = iio_priv(iio_dev);
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+
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/* Check for invalid channel */
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/* Check for invalid channel */
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if (chan->channel > LRADC_MAX_TOTAL_CHANS)
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if (chan->channel > LRADC_MAX_TOTAL_CHANS)
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return -EINVAL;
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return -EINVAL;
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@@ -857,7 +904,9 @@ static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
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return IIO_VAL_INT_PLUS_MICRO;
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return IIO_VAL_INT_PLUS_MICRO;
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}
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}
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- return -EINVAL;
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+ *val = lradc->vref_mv[chan->channel];
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+ *val2 = chan->scan_type.realbits;
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+ return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_CHAN_INFO_OFFSET:
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case IIO_CHAN_INFO_OFFSET:
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if (chan->type == IIO_TEMP) {
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if (chan->type == IIO_TEMP) {
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@@ -1189,7 +1238,8 @@ static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
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.type = (chan_type), \
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.type = (chan_type), \
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.indexed = 1, \
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.indexed = 1, \
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.scan_index = (idx), \
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.scan_index = (idx), \
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- .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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+ BIT(IIO_CHAN_INFO_SCALE), \
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.channel = (idx), \
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.channel = (idx), \
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.scan_type = { \
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.scan_type = { \
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.sign = 'u', \
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.sign = 'u', \
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@@ -1381,6 +1431,8 @@ static int mxs_lradc_probe(struct platform_device *pdev)
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return ret;
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return ret;
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}
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}
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+ lradc->vref_mv = of_cfg->vref_mv;
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+
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platform_set_drvdata(pdev, iio);
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platform_set_drvdata(pdev, iio);
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init_completion(&lradc->completion);
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init_completion(&lradc->completion);
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