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@@ -15,6 +15,8 @@
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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+#include <linux/irqdomain.h>
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+#include <linux/irq.h>
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#include "msm_drv.h"
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#include "mdp5_kms.h"
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@@ -82,18 +84,23 @@ irqreturn_t mdp5_irq(struct msm_kms *kms)
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{
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struct mdp_kms *mdp_kms = to_mdp_kms(kms);
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
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- struct msm_drm_private *priv = mdp5_kms->dev->dev_private;
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uint32_t intr;
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intr = mdp5_read(mdp5_kms, REG_MDP5_HW_INTR_STATUS);
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VERB("intr=%08x", intr);
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- if (intr & MDP5_HW_INTR_STATUS_INTR_MDP)
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+ if (intr & MDP5_HW_INTR_STATUS_INTR_MDP) {
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mdp5_irq_mdp(mdp_kms);
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+ intr &= ~MDP5_HW_INTR_STATUS_INTR_MDP;
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+ }
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- if (intr & MDP5_HW_INTR_STATUS_INTR_HDMI)
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- hdmi_irq(0, priv->hdmi);
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+ while (intr) {
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+ irq_hw_number_t hwirq = fls(intr) - 1;
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+ generic_handle_irq(irq_find_mapping(
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+ mdp5_kms->irqcontroller.domain, hwirq));
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+ intr &= ~(1 << hwirq);
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+ }
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return IRQ_HANDLED;
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}
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@@ -110,3 +117,82 @@ void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
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mdp_update_vblank_mask(to_mdp_kms(kms),
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mdp5_crtc_vblank(crtc), false);
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}
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+
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+/*
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+ * interrupt-controller implementation, so sub-blocks (hdmi/eDP/dsi/etc)
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+ * can register to get their irq's delivered
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+ */
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+
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+#define VALID_IRQS (MDP5_HW_INTR_STATUS_INTR_DSI0 | \
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+ MDP5_HW_INTR_STATUS_INTR_DSI1 | \
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+ MDP5_HW_INTR_STATUS_INTR_HDMI | \
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+ MDP5_HW_INTR_STATUS_INTR_EDP)
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+
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+static void mdp5_hw_mask_irq(struct irq_data *irqd)
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+{
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+ struct mdp5_kms *mdp5_kms = irq_data_get_irq_chip_data(irqd);
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+ smp_mb__before_atomic();
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+ clear_bit(irqd->hwirq, &mdp5_kms->irqcontroller.enabled_mask);
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+ smp_mb__after_atomic();
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+}
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+
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+static void mdp5_hw_unmask_irq(struct irq_data *irqd)
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+{
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+ struct mdp5_kms *mdp5_kms = irq_data_get_irq_chip_data(irqd);
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+ smp_mb__before_atomic();
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+ set_bit(irqd->hwirq, &mdp5_kms->irqcontroller.enabled_mask);
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+ smp_mb__after_atomic();
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+}
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+
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+static struct irq_chip mdp5_hw_irq_chip = {
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+ .name = "mdp5",
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+ .irq_mask = mdp5_hw_mask_irq,
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+ .irq_unmask = mdp5_hw_unmask_irq,
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+};
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+
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+static int mdp5_hw_irqdomain_map(struct irq_domain *d,
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+ unsigned int irq, irq_hw_number_t hwirq)
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+{
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+ struct mdp5_kms *mdp5_kms = d->host_data;
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+
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+ if (!(VALID_IRQS & (1 << hwirq)))
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+ return -EPERM;
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+
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+ irq_set_chip_and_handler(irq, &mdp5_hw_irq_chip, handle_level_irq);
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+ irq_set_chip_data(irq, mdp5_kms);
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+ set_irq_flags(irq, IRQF_VALID);
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+
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+ return 0;
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+}
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+
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+static struct irq_domain_ops mdp5_hw_irqdomain_ops = {
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+ .map = mdp5_hw_irqdomain_map,
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+ .xlate = irq_domain_xlate_onecell,
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+};
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+
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+
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+int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms)
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+{
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+ struct device *dev = mdp5_kms->dev->dev;
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+ struct irq_domain *d;
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+
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+ d = irq_domain_add_linear(dev->of_node, 32,
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+ &mdp5_hw_irqdomain_ops, mdp5_kms);
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+ if (!d) {
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+ dev_err(dev, "mdp5 irq domain add failed\n");
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+ return -ENXIO;
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+ }
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+
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+ mdp5_kms->irqcontroller.enabled_mask = 0;
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+ mdp5_kms->irqcontroller.domain = d;
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+
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+ return 0;
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+}
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+
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+void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms)
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+{
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+ if (mdp5_kms->irqcontroller.domain) {
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+ irq_domain_remove(mdp5_kms->irqcontroller.domain);
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+ mdp5_kms->irqcontroller.domain = NULL;
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+ }
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+}
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