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@@ -139,6 +139,11 @@ static int stm32f4_adc_clk_sel(struct platform_device *pdev,
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}
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rate = clk_get_rate(priv->aclk);
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+ if (!rate) {
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+ dev_err(&pdev->dev, "Invalid clock rate: 0\n");
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+ return -EINVAL;
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+ }
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+
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for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
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if ((rate / stm32f4_pclk_div[i]) <= STM32F4_ADC_MAX_CLK_RATE)
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break;
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@@ -216,6 +221,10 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
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* From spec: PLL output musn't exceed max rate
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*/
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rate = clk_get_rate(priv->aclk);
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+ if (!rate) {
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+ dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
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+ return -EINVAL;
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+ }
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for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
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ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
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@@ -232,6 +241,10 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
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/* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
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rate = clk_get_rate(priv->bclk);
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+ if (!rate) {
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+ dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
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+ return -EINVAL;
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+ }
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for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
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ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
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