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@@ -3102,7 +3102,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
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unsigned width;
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unsigned width;
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u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
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u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
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u32 hptxfsiz, grxfsiz, gnptxfsiz;
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u32 hptxfsiz, grxfsiz, gnptxfsiz;
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- u32 gusbcfg;
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+ u32 gusbcfg = 0;
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/*
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/*
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* Attempt to ensure this device is really a DWC_otg Controller.
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* Attempt to ensure this device is really a DWC_otg Controller.
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@@ -3135,8 +3135,8 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
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dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
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dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
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/* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */
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/* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */
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- gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
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- if (!(gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
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+ if (hsotg->dr_mode != USB_DR_MODE_HOST) {
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+ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
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dwc2_writel(gusbcfg | GUSBCFG_FORCEHOSTMODE,
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dwc2_writel(gusbcfg | GUSBCFG_FORCEHOSTMODE,
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hsotg->regs + GUSBCFG);
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hsotg->regs + GUSBCFG);
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usleep_range(100000, 150000);
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usleep_range(100000, 150000);
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@@ -3146,7 +3146,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
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hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
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hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
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dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
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dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
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dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
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dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
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- if (!(gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
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+ if (hsotg->dr_mode != USB_DR_MODE_HOST) {
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dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
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dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
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usleep_range(100000, 150000);
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usleep_range(100000, 150000);
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}
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}
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