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@@ -263,6 +263,24 @@ static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
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chip->irq_eoi(data);
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chip->irq_eoi(data);
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}
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}
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+static void lnw_irq_init_hw(struct lnw_gpio *lnw)
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+{
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+ void __iomem *reg;
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+ unsigned base;
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+
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+ for (base = 0; base < lnw->chip.ngpio; base += 32) {
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+ /* Clear the rising-edge detect register */
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+ reg = gpio_reg(&lnw->chip, base, GRER);
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+ writel(0, reg);
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+ /* Clear the falling-edge detect register */
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+ reg = gpio_reg(&lnw->chip, base, GFER);
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+ writel(0, reg);
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+ /* Clear the edge detect status register */
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+ reg = gpio_reg(&lnw->chip, base, GEDR);
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+ writel(~0, reg);
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+ }
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+}
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+
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#ifdef CONFIG_PM
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#ifdef CONFIG_PM
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static int lnw_gpio_runtime_resume(struct device *dev)
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static int lnw_gpio_runtime_resume(struct device *dev)
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{
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{
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@@ -371,6 +389,9 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
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dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
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dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
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goto err4;
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goto err4;
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}
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}
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+
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+ lnw_irq_init_hw(lnw);
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+
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irq_set_handler_data(pdev->irq, lnw);
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irq_set_handler_data(pdev->irq, lnw);
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irq_set_chained_handler(pdev->irq, lnw_irq_handler);
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irq_set_chained_handler(pdev->irq, lnw_irq_handler);
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for (i = 0; i < lnw->chip.ngpio; i++) {
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for (i = 0; i < lnw->chip.ngpio; i++) {
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