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@@ -207,6 +207,12 @@ static const u32 golden_settings_gc_9_1_rv1[] =
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SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
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};
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+static const u32 golden_settings_gc_9_x_common[] =
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+{
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+ SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_INDEX), 0xffffffff, 0x00000000,
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+ SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_DATA), 0xffffffff, 0x2544c382
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+};
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+
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#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
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#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
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@@ -242,6 +248,9 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
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default:
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break;
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}
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+
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+ amdgpu_program_register_sequence(adev, golden_settings_gc_9_x_common,
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+ (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
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}
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static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
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