x86/smpboot: Skip delays during SMP initialization similar to Xen

Remove the per-CPU delays during SMP initialization, which seems
to be possible on newer architectures with an x2APIC.

Xen does this since 2011. In fact, this commit is basically a
combination of the following Xen commits. The first removes the
delays, the second fixes an issue with the removal:

  commit 68fce206f6dba9981e8322269db49692c95ce250
  Author: Tim Deegan <Tim.Deegan@citrix.com>
  Date:   Tue Jul 19 14:13:01 2011 +0100

    x86: Remove timeouts from INIT-SIPI-SIPI sequence when using x2apic.

    Some of the timeouts are pointless since they're waiting for the ICR
    to ack the IPI delivery and that doesn't happen on x2apic.
    The others should be benign (and are suggested in the SDM) but
    removing them makes AP bringup much more reliable on some test boxes.

    Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>

  commit f12ee533150761df5a7099c83f2a5fa6c07d1187
  Author: Gang Wei <gang.wei@intel.com>
  Date:   Thu Dec 29 10:07:54 2011 +0000

    X86: Add a delay between INIT & SIPIs for tboot AP bring-up in X2APIC case

    Without this delay, Xen could not bring APs up while working with
    TXT/tboot, because tboot needs some time in APs to handle INIT before
    becoming ready for receiving SIPIs (this delay was removed as part of
    c/s 23724 by Tim Deegan).

    Signed-off-by: Gang Wei <gang.wei@intel.com>
    Acked-by: Keir Fraser <keir@xen.org>
    Acked-by: Tim Deegan <tim@xen.org>
    Committed-by: Tim Deegan <tim@xen.org>

Signed-off-by: Jan H. Schönherr <jschoenh@amazon.de>
Cc: Anthony Liguori <aliguori@amazon.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Gang Wei <gang.wei@intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Len Brown <len.brown@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tim Deegan <tim@xen.org>
Link: http://lkml.kernel.org/r/1430732554-7294-1-git-send-email-jschoenh@amazon.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>

arch/x86/kernel/smpboot.c

@@ -555,7 +555,7 @@ wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
 static int
 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
 {
-	unsigned long send_status, accept_status = 0;
+	unsigned long send_status = 0, accept_status = 0;
 	int maxlvt, num_starts, j;
 
 	maxlvt = lapic_get_maxlvt();
@@ -580,22 +580,34 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
 	apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
 		       phys_apicid);
 
-	pr_debug("Waiting for send to finish...\n");
-	send_status = safe_apic_wait_icr_idle();
+	if (!cpu_has_x2apic) {
+		pr_debug("Waiting for send to finish...\n");
+		send_status = safe_apic_wait_icr_idle();
 
-	mdelay(10);
+		mdelay(10);
 
-	pr_debug("Deasserting INIT\n");
+		pr_debug("Deasserting INIT\n");
 
-	/* Target chip */
-	/* Send IPI */
-	apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
+		/* Target chip */
+		/* Send IPI */
+		apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
 
-	pr_debug("Waiting for send to finish...\n");
-	send_status = safe_apic_wait_icr_idle();
+		pr_debug("Waiting for send to finish...\n");
+		send_status = safe_apic_wait_icr_idle();
 
-	mb();
-	atomic_set(&init_deasserted, 1);
+		mb();
+		atomic_set(&init_deasserted, 1);
+	} else if (tboot_enabled()) {
+		/*
+		 * With tboot AP is actually spinning in a mini-guest before
+		 * receiving INIT. Upon receiving INIT ipi, AP need time to
+		 * VMExit, update VMCS to tracking SIPIs and VMResume.
+		 *
+		 * While AP is in root mode handling the INIT the CPU will drop
+		 * any SIPIs
+		 */
+		udelay(10);
+	}
 
 	/*
 	 * Should we send STARTUP IPIs ?
@@ -637,20 +649,23 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
 		apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
 			       phys_apicid);
 
-		/*
-		 * Give the other CPU some time to accept the IPI.
-		 */
-		udelay(300);
+		if (!cpu_has_x2apic) {
+			/*
+			 * Give the other CPU some time to accept the IPI.
+			 */
+			udelay(300);
 
-		pr_debug("Startup point 1\n");
+			pr_debug("Startup point 1\n");
 
-		pr_debug("Waiting for send to finish...\n");
-		send_status = safe_apic_wait_icr_idle();
+			pr_debug("Waiting for send to finish...\n");
+			send_status = safe_apic_wait_icr_idle();
+
+			/*
+			 * Give the other CPU some time to accept the IPI.
+			 */
+			udelay(200);
+		}
 
-		/*
-		 * Give the other CPU some time to accept the IPI.
-		 */
-		udelay(200);
 		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP.  */
 			apic_write(APIC_ESR, 0);
 		accept_status = (apic_read(APIC_ESR) & 0xEF);