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@@ -445,7 +445,7 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev,
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aw_reg_add_dword /= sizeof(uint32_t);
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aw_reg_add_dword /= sizeof(uint32_t);
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packets_vec[0].bitfields2.reg_offset =
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packets_vec[0].bitfields2.reg_offset =
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- aw_reg_add_dword - CONFIG_REG_BASE;
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+ aw_reg_add_dword - AMD_CONFIG_REG_BASE;
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packets_vec[0].reg_data[0] = cntl.u32All;
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packets_vec[0].reg_data[0] = cntl.u32All;
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@@ -458,7 +458,7 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev,
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aw_reg_add_dword /= sizeof(uint32_t);
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aw_reg_add_dword /= sizeof(uint32_t);
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packets_vec[1].bitfields2.reg_offset =
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packets_vec[1].bitfields2.reg_offset =
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- aw_reg_add_dword - CONFIG_REG_BASE;
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+ aw_reg_add_dword - AMD_CONFIG_REG_BASE;
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packets_vec[1].reg_data[0] = addrHi.u32All;
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packets_vec[1].reg_data[0] = addrHi.u32All;
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aw_reg_add_dword =
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aw_reg_add_dword =
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@@ -470,7 +470,7 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev,
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aw_reg_add_dword /= sizeof(uint32_t);
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aw_reg_add_dword /= sizeof(uint32_t);
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packets_vec[2].bitfields2.reg_offset =
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packets_vec[2].bitfields2.reg_offset =
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- aw_reg_add_dword - CONFIG_REG_BASE;
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+ aw_reg_add_dword - AMD_CONFIG_REG_BASE;
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packets_vec[2].reg_data[0] = addrLo.u32All;
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packets_vec[2].reg_data[0] = addrLo.u32All;
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/* enable watch flag if address is not zero*/
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/* enable watch flag if address is not zero*/
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@@ -488,7 +488,7 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev,
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aw_reg_add_dword /= sizeof(uint32_t);
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aw_reg_add_dword /= sizeof(uint32_t);
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packets_vec[3].bitfields2.reg_offset =
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packets_vec[3].bitfields2.reg_offset =
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- aw_reg_add_dword - CONFIG_REG_BASE;
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+ aw_reg_add_dword - AMD_CONFIG_REG_BASE;
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packets_vec[3].reg_data[0] = cntl.u32All;
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packets_vec[3].reg_data[0] = cntl.u32All;
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status = dbgdev_diq_submit_ib(
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status = dbgdev_diq_submit_ib(
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@@ -690,7 +690,7 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev,
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packets_vec[1].header.opcode = IT_SET_CONFIG_REG;
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packets_vec[1].header.opcode = IT_SET_CONFIG_REG;
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packets_vec[1].header.type = PM4_TYPE_3;
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packets_vec[1].header.type = PM4_TYPE_3;
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packets_vec[1].bitfields2.reg_offset = SQ_CMD / (sizeof(uint32_t)) -
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packets_vec[1].bitfields2.reg_offset = SQ_CMD / (sizeof(uint32_t)) -
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- CONFIG_REG_BASE;
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+ AMD_CONFIG_REG_BASE;
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packets_vec[1].bitfields2.vmid_shift = SQ_CMD_VMID_OFFSET;
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packets_vec[1].bitfields2.vmid_shift = SQ_CMD_VMID_OFFSET;
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packets_vec[1].bitfields2.insert_vmid = 1;
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packets_vec[1].bitfields2.insert_vmid = 1;
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