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@@ -228,6 +228,43 @@ static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
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return clock_period_ps;
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}
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+static void ni_tio_set_bits_transient(struct ni_gpct *counter,
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+ enum ni_gpct_register reg,
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+ unsigned int mask, unsigned int value,
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+ unsigned int transient)
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+{
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+ struct ni_gpct_device *counter_dev = counter->counter_dev;
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+ unsigned long flags;
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+
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+ if (reg < NITIO_NUM_REGS) {
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+ spin_lock_irqsave(&counter_dev->regs_lock, flags);
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+ counter_dev->regs[reg] &= ~mask;
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+ counter_dev->regs[reg] |= (value & mask);
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+ write_register(counter, counter_dev->regs[reg] | transient,
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+ reg);
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+ mmiowb();
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+ spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
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+ }
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+}
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+
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+/**
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+ * ni_tio_set_bits() - Safely write a counter register.
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+ * @counter: struct ni_gpct counter.
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+ * @reg: the register to write.
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+ * @mask: the bits to change.
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+ * @value: the new bits value.
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+ *
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+ * Used to write to, and update the software copy, a register whose bits may
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+ * be twiddled in interrupt context, or whose software copy may be read in
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+ * interrupt context.
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+ */
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+void ni_tio_set_bits(struct ni_gpct *counter, enum ni_gpct_register reg,
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+ unsigned int mask, unsigned int value)
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+{
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+ ni_tio_set_bits_transient(counter, reg, mask, value, 0x0);
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+}
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+EXPORT_SYMBOL_GPL(ni_tio_set_bits);
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+
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/**
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* ni_tio_get_soft_copy() - Safely read the software copy of a counter register.
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* @counter: struct ni_gpct counter.
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