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@@ -1920,20 +1920,21 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
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DP_TRAIN_VOLTAGE_SWING_MASK;
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}
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-static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
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- u32 level, enum port port, int type)
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+static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
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+ int level, enum intel_output_type type)
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{
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- const struct cnl_ddi_buf_trans *ddi_translations = NULL;
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- u32 n_entries, val;
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- int ln;
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+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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+ enum port port = intel_ddi_get_encoder_port(encoder);
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+ const struct cnl_ddi_buf_trans *ddi_translations;
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+ int n_entries, ln;
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+ u32 val;
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- if (type == INTEL_OUTPUT_HDMI) {
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+ if (type == INTEL_OUTPUT_HDMI)
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ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
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- } else if (type == INTEL_OUTPUT_DP) {
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- ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
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- } else if (type == INTEL_OUTPUT_EDP) {
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+ else if (type == INTEL_OUTPUT_EDP)
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ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
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- }
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+ else
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+ ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
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if (WARN_ON(ddi_translations == NULL))
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return;
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@@ -1986,26 +1987,22 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
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I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
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}
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-static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
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+static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
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+ int level, enum intel_output_type type)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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- struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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enum port port = intel_ddi_get_encoder_port(encoder);
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- int type = encoder->type;
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- int width = 0;
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- int rate = 0;
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+ int width, rate, ln;
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u32 val;
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- int ln = 0;
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- if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) {
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- width = intel_dp->lane_count;
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- rate = intel_dp->link_rate;
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- } else if (type == INTEL_OUTPUT_HDMI) {
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+ if (type == INTEL_OUTPUT_HDMI) {
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width = 4;
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- /* Rate is always < than 6GHz for HDMI */
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+ rate = 0; /* Rate is always < than 6GHz for HDMI */
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} else {
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- MISSING_CASE(type);
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- return;
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+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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+
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+ width = intel_dp->lane_count;
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+ rate = intel_dp->link_rate;
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}
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/*
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@@ -2014,7 +2011,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
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* else clear to 0b.
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*/
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val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
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- if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
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+ if (type != INTEL_OUTPUT_HDMI)
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val |= COMMON_KEEPER_EN;
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else
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val &= ~COMMON_KEEPER_EN;
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@@ -2049,7 +2046,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
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I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
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/* 5. Program swing and de-emphasis */
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- cnl_ddi_vswing_program(dev_priv, level, port, type);
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+ cnl_ddi_vswing_program(encoder, level, type);
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/* 6. Set training enable to trigger update */
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val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
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@@ -2089,7 +2086,7 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp)
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u32 level = intel_ddi_dp_level(intel_dp);
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if (IS_CANNONLAKE(dev_priv))
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- cnl_ddi_vswing_sequence(encoder, level);
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+ cnl_ddi_vswing_sequence(encoder, level, encoder->type);
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else
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bxt_ddi_vswing_sequence(encoder, level, encoder->type);
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@@ -2187,7 +2184,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
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intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
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if (IS_CANNONLAKE(dev_priv))
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- cnl_ddi_vswing_sequence(encoder, level);
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+ cnl_ddi_vswing_sequence(encoder, level, encoder->type);
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else if (IS_GEN9_LP(dev_priv))
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bxt_ddi_vswing_sequence(encoder, level, encoder->type);
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else
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@@ -2218,7 +2215,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
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intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
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if (IS_CANNONLAKE(dev_priv))
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- cnl_ddi_vswing_sequence(encoder, level);
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+ cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
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else if (IS_GEN9_LP(dev_priv))
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bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
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else
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