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@@ -0,0 +1,558 @@
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+/*
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+ * OMAP DPLL clock support
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+ *
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+ * Copyright (C) 2013 Texas Instruments, Inc.
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+ *
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+ * Tero Kristo <t-kristo@ti.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
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+ * kind, whether express or implied; without even the implied warranty
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+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/clk-provider.h>
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+#include <linux/slab.h>
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+#include <linux/err.h>
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+#include <linux/clk/ti.h>
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+
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+#undef pr_fmt
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+#define pr_fmt(fmt) "%s: " fmt, __func__
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+
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+#define DPLL_HAS_AUTOIDLE 0x1
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+
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+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
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+ defined(CONFIG_SOC_DRA7XX)
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+static const struct clk_ops dpll_m4xen_ck_ops = {
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+ .enable = &omap3_noncore_dpll_enable,
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+ .disable = &omap3_noncore_dpll_disable,
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+ .recalc_rate = &omap4_dpll_regm4xen_recalc,
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+ .round_rate = &omap4_dpll_regm4xen_round_rate,
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+ .set_rate = &omap3_noncore_dpll_set_rate,
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+ .get_parent = &omap2_init_dpll_parent,
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+};
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+#endif
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+
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+static const struct clk_ops dpll_core_ck_ops = {
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+ .recalc_rate = &omap3_dpll_recalc,
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+ .get_parent = &omap2_init_dpll_parent,
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+};
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+
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+#ifdef CONFIG_ARCH_OMAP3
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+static const struct clk_ops omap3_dpll_core_ck_ops = {
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+ .get_parent = &omap2_init_dpll_parent,
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+ .recalc_rate = &omap3_dpll_recalc,
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+ .round_rate = &omap2_dpll_round_rate,
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+};
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+#endif
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+
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+static const struct clk_ops dpll_ck_ops = {
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+ .enable = &omap3_noncore_dpll_enable,
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+ .disable = &omap3_noncore_dpll_disable,
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+ .recalc_rate = &omap3_dpll_recalc,
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+ .round_rate = &omap2_dpll_round_rate,
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+ .set_rate = &omap3_noncore_dpll_set_rate,
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+ .get_parent = &omap2_init_dpll_parent,
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+};
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+
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+static const struct clk_ops dpll_no_gate_ck_ops = {
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+ .recalc_rate = &omap3_dpll_recalc,
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+ .get_parent = &omap2_init_dpll_parent,
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+ .round_rate = &omap2_dpll_round_rate,
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+ .set_rate = &omap3_noncore_dpll_set_rate,
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+};
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+
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+#ifdef CONFIG_ARCH_OMAP3
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+static const struct clk_ops omap3_dpll_ck_ops = {
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+ .enable = &omap3_noncore_dpll_enable,
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+ .disable = &omap3_noncore_dpll_disable,
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+ .get_parent = &omap2_init_dpll_parent,
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+ .recalc_rate = &omap3_dpll_recalc,
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+ .set_rate = &omap3_noncore_dpll_set_rate,
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+ .round_rate = &omap2_dpll_round_rate,
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+};
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+
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+static const struct clk_ops omap3_dpll_per_ck_ops = {
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+ .enable = &omap3_noncore_dpll_enable,
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+ .disable = &omap3_noncore_dpll_disable,
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+ .get_parent = &omap2_init_dpll_parent,
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+ .recalc_rate = &omap3_dpll_recalc,
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+ .set_rate = &omap3_dpll4_set_rate,
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+ .round_rate = &omap2_dpll_round_rate,
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+};
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+#endif
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+
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+static const struct clk_ops dpll_x2_ck_ops = {
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+ .recalc_rate = &omap3_clkoutx2_recalc,
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+};
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+
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+/**
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+ * ti_clk_register_dpll - low level registration of a DPLL clock
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+ * @hw: hardware clock definition for the clock
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+ * @node: device node for the clock
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+ *
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+ * Finalizes DPLL registration process. In case a failure (clk-ref or
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+ * clk-bypass is missing), the clock is added to retry list and
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+ * the initialization is retried on later stage.
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+ */
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+static void __init ti_clk_register_dpll(struct clk_hw *hw,
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+ struct device_node *node)
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+{
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+ struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
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+ struct dpll_data *dd = clk_hw->dpll_data;
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+ struct clk *clk;
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+
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+ dd->clk_ref = of_clk_get(node, 0);
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+ dd->clk_bypass = of_clk_get(node, 1);
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+
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+ if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) {
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+ pr_debug("clk-ref or clk-bypass missing for %s, retry later\n",
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+ node->name);
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+ if (!ti_clk_retry_init(node, hw, ti_clk_register_dpll))
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+ return;
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+
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+ goto cleanup;
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+ }
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+
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+ /* register the clock */
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+ clk = clk_register(NULL, &clk_hw->hw);
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+
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+ if (!IS_ERR(clk)) {
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+ omap2_init_clk_hw_omap_clocks(clk);
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+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
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+ kfree(clk_hw->hw.init->parent_names);
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+ kfree(clk_hw->hw.init);
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+ return;
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+ }
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+
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+cleanup:
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+ kfree(clk_hw->dpll_data);
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+ kfree(clk_hw->hw.init->parent_names);
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+ kfree(clk_hw->hw.init);
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+ kfree(clk_hw);
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+}
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+
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+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
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+ defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX)
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+/**
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+ * ti_clk_register_dpll_x2 - Registers a DPLLx2 clock
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+ * @node: device node for this clock
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+ * @ops: clk_ops for this clock
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+ * @hw_ops: clk_hw_ops for this clock
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+ *
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+ * Initializes a DPLL x 2 clock from device tree data.
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+ */
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+static void ti_clk_register_dpll_x2(struct device_node *node,
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+ const struct clk_ops *ops,
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+ const struct clk_hw_omap_ops *hw_ops)
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+{
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+ struct clk *clk;
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+ struct clk_init_data init = { NULL };
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+ struct clk_hw_omap *clk_hw;
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+ const char *name = node->name;
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+ const char *parent_name;
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+
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+ parent_name = of_clk_get_parent_name(node, 0);
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+ if (!parent_name) {
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+ pr_err("%s must have parent\n", node->name);
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+ return;
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+ }
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+
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+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
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+ if (!clk_hw)
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+ return;
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+
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+ clk_hw->ops = hw_ops;
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+ clk_hw->hw.init = &init;
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+
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+ init.name = name;
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+ init.ops = ops;
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+ init.parent_names = &parent_name;
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+ init.num_parents = 1;
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+
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+ /* register the clock */
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+ clk = clk_register(NULL, &clk_hw->hw);
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+
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+ if (IS_ERR(clk)) {
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+ kfree(clk_hw);
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+ } else {
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+ omap2_init_clk_hw_omap_clocks(clk);
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+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
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+ }
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+}
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+#endif
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+
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+/**
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+ * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
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+ * @node: device node containing the DPLL info
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+ * @ops: ops for the DPLL
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+ * @ddt: DPLL data template to use
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+ * @init_flags: flags for controlling init types
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+ *
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+ * Initializes a DPLL clock from device tree data.
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+ */
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+static void __init of_ti_dpll_setup(struct device_node *node,
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+ const struct clk_ops *ops,
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+ const struct dpll_data *ddt,
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+ u8 init_flags)
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+{
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+ struct clk_hw_omap *clk_hw = NULL;
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+ struct clk_init_data *init = NULL;
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+ const char **parent_names = NULL;
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+ struct dpll_data *dd = NULL;
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+ int i;
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+ u8 dpll_mode = 0;
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+
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+ dd = kzalloc(sizeof(*dd), GFP_KERNEL);
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+ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
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+ init = kzalloc(sizeof(*init), GFP_KERNEL);
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+ if (!dd || !clk_hw || !init)
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+ goto cleanup;
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+
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+ memcpy(dd, ddt, sizeof(*dd));
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+
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+ clk_hw->dpll_data = dd;
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+ clk_hw->ops = &clkhwops_omap3_dpll;
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+ clk_hw->hw.init = init;
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+ clk_hw->flags = MEMMAP_ADDRESSING;
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+
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+ init->name = node->name;
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+ init->ops = ops;
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+
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+ init->num_parents = of_clk_get_parent_count(node);
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+ if (init->num_parents < 1) {
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+ pr_err("%s must have parent(s)\n", node->name);
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+ goto cleanup;
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+ }
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+
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+ parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
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+ if (!parent_names)
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+ goto cleanup;
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+
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+ for (i = 0; i < init->num_parents; i++)
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+ parent_names[i] = of_clk_get_parent_name(node, i);
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+
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+ init->parent_names = parent_names;
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+
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+ dd->control_reg = ti_clk_get_reg_addr(node, 0);
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+ dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
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+ dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
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+
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+ if (!dd->control_reg || !dd->idlest_reg || !dd->mult_div1_reg)
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+ goto cleanup;
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+
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+ if (init_flags & DPLL_HAS_AUTOIDLE) {
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+ dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
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+ if (!dd->autoidle_reg)
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+ goto cleanup;
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+ }
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+
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+ if (of_property_read_bool(node, "ti,low-power-stop"))
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+ dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
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+
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+ if (of_property_read_bool(node, "ti,low-power-bypass"))
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+ dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
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+
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+ if (of_property_read_bool(node, "ti,lock"))
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+ dpll_mode |= 1 << DPLL_LOCKED;
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+
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+ if (dpll_mode)
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+ dd->modes = dpll_mode;
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+
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+ ti_clk_register_dpll(&clk_hw->hw, node);
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+ return;
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+
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+cleanup:
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+ kfree(dd);
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+ kfree(parent_names);
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+ kfree(init);
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+ kfree(clk_hw);
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+}
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+
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+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
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+ defined(CONFIG_SOC_DRA7XX)
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+static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
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+{
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+ ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
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+}
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+CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
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+ of_ti_omap4_dpll_x2_setup);
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+#endif
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+
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+#ifdef CONFIG_SOC_AM33XX
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+static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
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+{
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+ ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
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+}
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+CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
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+ of_ti_am3_dpll_x2_setup);
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+#endif
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+
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+#ifdef CONFIG_ARCH_OMAP3
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+static void __init of_ti_omap3_dpll_setup(struct device_node *node)
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+{
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+ const struct dpll_data dd = {
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+ .idlest_mask = 0x1,
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+ .enable_mask = 0x7,
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+ .autoidle_mask = 0x7,
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+ .mult_mask = 0x7ff << 8,
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+ .div1_mask = 0x7f,
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+ .max_multiplier = 2047,
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+ .max_divider = 128,
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+ .min_divider = 1,
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+ .freqsel_mask = 0xf0,
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+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
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+ };
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+
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+ of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
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+}
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+CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
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+ of_ti_omap3_dpll_setup);
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+
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+static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
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+{
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+ const struct dpll_data dd = {
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+ .idlest_mask = 0x1,
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+ .enable_mask = 0x7,
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+ .autoidle_mask = 0x7,
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+ .mult_mask = 0x7ff << 16,
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+ .div1_mask = 0x7f << 8,
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+ .max_multiplier = 2047,
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+ .max_divider = 128,
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+ .min_divider = 1,
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+ .freqsel_mask = 0xf0,
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+ };
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+
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+ of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
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+}
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+CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
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+ of_ti_omap3_core_dpll_setup);
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+
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+static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
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+{
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+ const struct dpll_data dd = {
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+ .idlest_mask = 0x1 << 1,
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+ .enable_mask = 0x7 << 16,
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+ .autoidle_mask = 0x7 << 3,
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+ .mult_mask = 0x7ff << 8,
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+ .div1_mask = 0x7f,
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+ .max_multiplier = 2047,
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+ .max_divider = 128,
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+ .min_divider = 1,
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+ .freqsel_mask = 0xf00000,
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+ .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
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+ };
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+
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+ of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
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+}
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+CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
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+ of_ti_omap3_per_dpll_setup);
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+
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+static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
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+{
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+ const struct dpll_data dd = {
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+ .idlest_mask = 0x1 << 1,
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+ .enable_mask = 0x7 << 16,
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+ .autoidle_mask = 0x7 << 3,
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+ .mult_mask = 0xfff << 8,
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+ .div1_mask = 0x7f,
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+ .max_multiplier = 4095,
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+ .max_divider = 128,
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+ .min_divider = 1,
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+ .sddiv_mask = 0xff << 24,
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+ .dco_mask = 0xe << 20,
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+ .flags = DPLL_J_TYPE,
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|
|
+ .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
|
|
|
+ };
|
|
|
+
|
|
|
+ of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
|
|
|
+}
|
|
|
+CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
|
|
|
+ of_ti_omap3_per_jtype_dpll_setup);
|
|
|
+#endif
|
|
|
+
|
|
|
+static void __init of_ti_omap4_dpll_setup(struct device_node *node)
|
|
|
+{
|
|
|
+ const struct dpll_data dd = {
|
|
|
+ .idlest_mask = 0x1,
|
|
|
+ .enable_mask = 0x7,
|
|
|
+ .autoidle_mask = 0x7,
|
|
|
+ .mult_mask = 0x7ff << 8,
|
|
|
+ .div1_mask = 0x7f,
|
|
|
+ .max_multiplier = 2047,
|
|
|
+ .max_divider = 128,
|
|
|
+ .min_divider = 1,
|
|
|
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
|
|
+ };
|
|
|
+
|
|
|
+ of_ti_dpll_setup(node, &dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
|
|
|
+}
|
|
|
+CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
|
|
|
+ of_ti_omap4_dpll_setup);
|
|
|
+
|
|
|
+static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
|
|
|
+{
|
|
|
+ const struct dpll_data dd = {
|
|
|
+ .idlest_mask = 0x1,
|
|
|
+ .enable_mask = 0x7,
|
|
|
+ .autoidle_mask = 0x7,
|
|
|
+ .mult_mask = 0x7ff << 8,
|
|
|
+ .div1_mask = 0x7f,
|
|
|
+ .max_multiplier = 2047,
|
|
|
+ .max_divider = 128,
|
|
|
+ .min_divider = 1,
|
|
|
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
|
|
+ };
|
|
|
+
|
|
|
+ of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
|
|
|
+}
|
|
|
+CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
|
|
|
+ of_ti_omap4_core_dpll_setup);
|
|
|
+
|
|
|
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
|
|
|
+ defined(CONFIG_SOC_DRA7XX)
|
|
|
+static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
|
|
|
+{
|
|
|
+ const struct dpll_data dd = {
|
|
|
+ .idlest_mask = 0x1,
|
|
|
+ .enable_mask = 0x7,
|
|
|
+ .autoidle_mask = 0x7,
|
|
|
+ .mult_mask = 0x7ff << 8,
|
|
|
+ .div1_mask = 0x7f,
|
|
|
+ .max_multiplier = 2047,
|
|
|
+ .max_divider = 128,
|
|
|
+ .min_divider = 1,
|
|
|
+ .m4xen_mask = 0x800,
|
|
|
+ .lpmode_mask = 1 << 10,
|
|
|
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
|
|
+ };
|
|
|
+
|
|
|
+ of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
|
|
|
+}
|
|
|
+CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
|
|
|
+ of_ti_omap4_m4xen_dpll_setup);
|
|
|
+
|
|
|
+static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
|
|
|
+{
|
|
|
+ const struct dpll_data dd = {
|
|
|
+ .idlest_mask = 0x1,
|
|
|
+ .enable_mask = 0x7,
|
|
|
+ .autoidle_mask = 0x7,
|
|
|
+ .mult_mask = 0xfff << 8,
|
|
|
+ .div1_mask = 0xff,
|
|
|
+ .max_multiplier = 4095,
|
|
|
+ .max_divider = 256,
|
|
|
+ .min_divider = 1,
|
|
|
+ .sddiv_mask = 0xff << 24,
|
|
|
+ .flags = DPLL_J_TYPE,
|
|
|
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
|
|
+ };
|
|
|
+
|
|
|
+ of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
|
|
|
+}
|
|
|
+CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
|
|
|
+ of_ti_omap4_jtype_dpll_setup);
|
|
|
+#endif
|
|
|
+
|
|
|
+static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
|
|
|
+{
|
|
|
+ const struct dpll_data dd = {
|
|
|
+ .idlest_mask = 0x1,
|
|
|
+ .enable_mask = 0x7,
|
|
|
+ .autoidle_mask = 0x7,
|
|
|
+ .mult_mask = 0x7ff << 8,
|
|
|
+ .div1_mask = 0x7f,
|
|
|
+ .max_multiplier = 2047,
|
|
|
+ .max_divider = 128,
|
|
|
+ .min_divider = 1,
|
|
|
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
|
|
+ };
|
|
|
+
|
|
|
+ of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
|
|
|
+}
|
|
|
+CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
|
|
|
+ of_ti_am3_no_gate_dpll_setup);
|
|
|
+
|
|
|
+static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
|
|
|
+{
|
|
|
+ const struct dpll_data dd = {
|
|
|
+ .idlest_mask = 0x1,
|
|
|
+ .enable_mask = 0x7,
|
|
|
+ .autoidle_mask = 0x7,
|
|
|
+ .mult_mask = 0x7ff << 8,
|
|
|
+ .div1_mask = 0x7f,
|
|
|
+ .max_multiplier = 4095,
|
|
|
+ .max_divider = 256,
|
|
|
+ .min_divider = 2,
|
|
|
+ .flags = DPLL_J_TYPE,
|
|
|
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
|
|
+ };
|
|
|
+
|
|
|
+ of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0);
|
|
|
+}
|
|
|
+CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
|
|
|
+ of_ti_am3_jtype_dpll_setup);
|
|
|
+
|
|
|
+static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
|
|
|
+{
|
|
|
+ const struct dpll_data dd = {
|
|
|
+ .idlest_mask = 0x1,
|
|
|
+ .enable_mask = 0x7,
|
|
|
+ .autoidle_mask = 0x7,
|
|
|
+ .mult_mask = 0x7ff << 8,
|
|
|
+ .div1_mask = 0x7f,
|
|
|
+ .max_multiplier = 2047,
|
|
|
+ .max_divider = 128,
|
|
|
+ .min_divider = 1,
|
|
|
+ .flags = DPLL_J_TYPE,
|
|
|
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
|
|
+ };
|
|
|
+
|
|
|
+ of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
|
|
|
+}
|
|
|
+CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
|
|
|
+ "ti,am3-dpll-no-gate-j-type-clock",
|
|
|
+ of_ti_am3_no_gate_jtype_dpll_setup);
|
|
|
+
|
|
|
+static void __init of_ti_am3_dpll_setup(struct device_node *node)
|
|
|
+{
|
|
|
+ const struct dpll_data dd = {
|
|
|
+ .idlest_mask = 0x1,
|
|
|
+ .enable_mask = 0x7,
|
|
|
+ .autoidle_mask = 0x7,
|
|
|
+ .mult_mask = 0x7ff << 8,
|
|
|
+ .div1_mask = 0x7f,
|
|
|
+ .max_multiplier = 2047,
|
|
|
+ .max_divider = 128,
|
|
|
+ .min_divider = 1,
|
|
|
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
|
|
+ };
|
|
|
+
|
|
|
+ of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0);
|
|
|
+}
|
|
|
+CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
|
|
|
+
|
|
|
+static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
|
|
|
+{
|
|
|
+ const struct dpll_data dd = {
|
|
|
+ .idlest_mask = 0x1,
|
|
|
+ .enable_mask = 0x7,
|
|
|
+ .autoidle_mask = 0x7,
|
|
|
+ .mult_mask = 0x7ff << 8,
|
|
|
+ .div1_mask = 0x7f,
|
|
|
+ .max_multiplier = 2047,
|
|
|
+ .max_divider = 128,
|
|
|
+ .min_divider = 1,
|
|
|
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
|
|
+ };
|
|
|
+
|
|
|
+ of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, 0);
|
|
|
+}
|
|
|
+CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
|
|
|
+ of_ti_am3_core_dpll_setup);
|
Tero Kristo