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@@ -41,6 +41,22 @@
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#include <linux/completion.h>
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#include <linux/completion.h>
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#include "debug.h"
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#include "debug.h"
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+#define MASKBYTE0 0xff
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+#define MASKBYTE1 0xff00
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+#define MASKBYTE2 0xff0000
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+#define MASKBYTE3 0xff000000
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+#define MASKHWORD 0xffff0000
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+#define MASKLWORD 0x0000ffff
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+#define MASKDWORD 0xffffffff
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+#define MASK12BITS 0xfff
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+#define MASKH4BITS 0xf0000000
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+#define MASKOFDM_D 0xffc00000
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+#define MASKCCK 0x3f3f3f3f
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+
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+#define MASK4BITS 0x0f
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+#define MASK20BITS 0xfffff
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+#define RFREG_OFFSET_MASK 0xfffff
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+
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#define RF_CHANGE_BY_INIT 0
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#define RF_CHANGE_BY_INIT 0
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#define RF_CHANGE_BY_IPS BIT(28)
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#define RF_CHANGE_BY_IPS BIT(28)
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#define RF_CHANGE_BY_PS BIT(29)
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#define RF_CHANGE_BY_PS BIT(29)
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@@ -87,7 +103,18 @@
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#define MAC80211_4ADDR_LEN 30
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#define MAC80211_4ADDR_LEN 30
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#define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
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#define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
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+#define CHANNEL_MAX_NUMBER_2G 14
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+#define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
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+ *"phy_GetChnlGroup8812A" and
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+ * "Hal_ReadTxPowerInfo8812A"
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+ */
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+#define CHANNEL_MAX_NUMBER_5G_80M 7
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#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
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#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
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+#define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
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+ *"phy_GetChnlGroup8812A" and
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+ * "Hal_ReadTxPowerInfo8812A"
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+ */
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+#define CHANNEL_MAX_NUMBER_5G_80M 7
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#define MAX_PG_GROUP 13
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#define MAX_PG_GROUP 13
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#define CHANNEL_GROUP_MAX_2G 3
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#define CHANNEL_GROUP_MAX_2G 3
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#define CHANNEL_GROUP_IDX_5GL 3
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#define CHANNEL_GROUP_IDX_5GL 3
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@@ -115,6 +142,11 @@
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#define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
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#define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
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#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
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#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
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+#define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
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+
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+#define DEL_SW_IDX_SZ 30
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+#define BAND_NUM 3
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+
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enum rf_tx_num {
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enum rf_tx_num {
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RF_1TX = 0,
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RF_1TX = 0,
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RF_2TX,
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RF_2TX,
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@@ -140,6 +172,8 @@ struct txpower_info_5g {
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u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
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u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
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u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
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u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
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u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
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u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
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+ u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
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+ u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
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};
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};
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enum rate_section {
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enum rate_section {
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@@ -186,6 +220,8 @@ enum hardware_type {
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HARDWARE_TYPE_RTL8723U,
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HARDWARE_TYPE_RTL8723U,
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HARDWARE_TYPE_RTL8723BE,
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HARDWARE_TYPE_RTL8723BE,
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HARDWARE_TYPE_RTL8188EE,
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HARDWARE_TYPE_RTL8188EE,
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+ HARDWARE_TYPE_RTL8821AE,
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+ HARDWARE_TYPE_RTL8812AE,
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/* keep it last */
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/* keep it last */
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HARDWARE_TYPE_NUM
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HARDWARE_TYPE_NUM
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@@ -230,6 +266,8 @@ enum hardware_type {
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enum scan_operation_backup_opt {
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enum scan_operation_backup_opt {
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SCAN_OPT_BACKUP = 0,
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SCAN_OPT_BACKUP = 0,
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+ SCAN_OPT_BACKUP_BAND0 = 0,
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+ SCAN_OPT_BACKUP_BAND1,
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SCAN_OPT_RESTORE,
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SCAN_OPT_RESTORE,
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SCAN_OPT_MAX
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SCAN_OPT_MAX
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};
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};
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@@ -264,7 +302,9 @@ struct bb_reg_def {
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enum io_type {
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enum io_type {
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IO_CMD_PAUSE_DM_BY_SCAN = 0,
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IO_CMD_PAUSE_DM_BY_SCAN = 0,
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- IO_CMD_RESUME_DM_BY_SCAN = 1,
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+ IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
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+ IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
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+ IO_CMD_RESUME_DM_BY_SCAN = 2,
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};
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};
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enum hw_variables {
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enum hw_variables {
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@@ -331,6 +371,7 @@ enum hw_variables {
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HW_VAR_SET_RPWM,
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HW_VAR_SET_RPWM,
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HW_VAR_H2C_FW_PWRMODE,
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HW_VAR_H2C_FW_PWRMODE,
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HW_VAR_H2C_FW_JOINBSSRPT,
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HW_VAR_H2C_FW_JOINBSSRPT,
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+ HW_VAR_H2C_FW_MEDIASTATUSRPT,
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HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
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HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
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HW_VAR_FW_PSMODE_STATUS,
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HW_VAR_FW_PSMODE_STATUS,
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HW_VAR_RESUME_CLK_ON,
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HW_VAR_RESUME_CLK_ON,
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@@ -364,6 +405,7 @@ enum hw_variables {
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HAL_DEF_WOWLAN,
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HAL_DEF_WOWLAN,
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HW_VAR_MRC,
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HW_VAR_MRC,
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HW_VAR_KEEP_ALIVE,
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HW_VAR_KEEP_ALIVE,
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+ HW_VAR_NAV_UPPER,
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HW_VAR_MGT_FILTER,
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HW_VAR_MGT_FILTER,
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HW_VAR_CTRL_FILTER,
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HW_VAR_CTRL_FILTER,
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@@ -423,6 +465,7 @@ enum hw_descs {
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HW_DESC_RXBUFF_ADDR,
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HW_DESC_RXBUFF_ADDR,
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HW_DESC_RXPKT_LEN,
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HW_DESC_RXPKT_LEN,
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HW_DESC_RXERO,
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HW_DESC_RXERO,
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+ HW_DESC_RX_PREPARE,
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};
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};
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enum prime_sc {
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enum prime_sc {
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@@ -441,6 +484,7 @@ enum rf_type {
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enum ht_channel_width {
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enum ht_channel_width {
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HT_CHANNEL_WIDTH_20 = 0,
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HT_CHANNEL_WIDTH_20 = 0,
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HT_CHANNEL_WIDTH_20_40 = 1,
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HT_CHANNEL_WIDTH_20_40 = 1,
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+ HT_CHANNEL_WIDTH_80 = 2,
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};
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};
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/* Ref: 802.11i sepc D10.0 7.3.2.25.1
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/* Ref: 802.11i sepc D10.0 7.3.2.25.1
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@@ -505,6 +549,9 @@ enum rtl_var_map {
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MAC_RCR_ACRC32,
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MAC_RCR_ACRC32,
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MAC_RCR_ACF,
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MAC_RCR_ACF,
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MAC_RCR_AAP,
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MAC_RCR_AAP,
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+ MAC_HIMR,
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+ MAC_HIMRE,
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+ MAC_HSISR,
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/*efuse map */
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/*efuse map */
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EFUSE_TEST,
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EFUSE_TEST,
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@@ -679,7 +726,9 @@ enum wireless_mode {
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WIRELESS_MODE_G = 0x04,
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WIRELESS_MODE_G = 0x04,
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WIRELESS_MODE_AUTO = 0x08,
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WIRELESS_MODE_AUTO = 0x08,
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WIRELESS_MODE_N_24G = 0x10,
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WIRELESS_MODE_N_24G = 0x10,
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- WIRELESS_MODE_N_5G = 0x20
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+ WIRELESS_MODE_N_5G = 0x20,
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+ WIRELESS_MODE_AC_5G = 0x40,
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+ WIRELESS_MODE_AC_24G = 0x80
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};
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};
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#define IS_WIRELESS_MODE_A(wirelessmode) \
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#define IS_WIRELESS_MODE_A(wirelessmode) \
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@@ -703,6 +752,8 @@ enum ratr_table_mode {
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RATR_INX_WIRELESS_B = 6,
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RATR_INX_WIRELESS_B = 6,
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RATR_INX_WIRELESS_MC = 7,
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RATR_INX_WIRELESS_MC = 7,
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RATR_INX_WIRELESS_A = 8,
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RATR_INX_WIRELESS_A = 8,
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+ RATR_INX_WIRELESS_AC_5N = 8,
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+ RATR_INX_WIRELESS_AC_24N = 9,
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};
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};
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enum rtl_link_state {
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enum rtl_link_state {
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@@ -837,8 +888,12 @@ struct wireless_stats {
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long signal_strength;
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long signal_strength;
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u8 rx_rssi_percentage[4];
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u8 rx_rssi_percentage[4];
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+ u8 rx_evm_dbm[4];
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u8 rx_evm_percentage[2];
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u8 rx_evm_percentage[2];
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+ u16 rx_cfo_short[4];
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+ u16 rx_cfo_tail[4];
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+
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struct rt_smooth_data ui_rssi;
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struct rt_smooth_data ui_rssi;
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struct rt_smooth_data ui_link_quality;
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struct rt_smooth_data ui_link_quality;
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};
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};
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@@ -867,6 +922,10 @@ struct rate_adaptive {
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u32 ping_rssi_thresh_for_ra;
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u32 ping_rssi_thresh_for_ra;
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u32 last_ratr;
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u32 last_ratr;
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u8 pre_ratr_state;
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u8 pre_ratr_state;
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+ u8 ldpc_thres;
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+ bool use_ldpc;
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+ bool lower_rts_rate;
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+ bool is_special_data;
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};
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};
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struct regd_pair_mapping {
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struct regd_pair_mapping {
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@@ -875,6 +934,16 @@ struct regd_pair_mapping {
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u16 reg_2ghz_ctl;
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u16 reg_2ghz_ctl;
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};
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};
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+struct dynamic_primary_cca {
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+ u8 pricca_flag;
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+ u8 intf_flag;
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+ u8 intf_type;
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+ u8 dup_rts_flag;
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+ u8 monitor_flag;
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+ u8 ch_offset;
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+ u8 mf_state;
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+};
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+
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struct rtl_regulatory {
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struct rtl_regulatory {
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char alpha2[2];
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char alpha2[2];
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u16 country_code;
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u16 country_code;
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@@ -1010,11 +1079,14 @@ struct rtl_phy {
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u32 iqk_bb_backup[10];
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u32 iqk_bb_backup[10];
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bool iqk_initialized;
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bool iqk_initialized;
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+ bool rfpath_rx_enable[MAX_RF_PATH];
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+ u8 reg_837;
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/* Dual mac */
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/* Dual mac */
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bool need_iqk;
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bool need_iqk;
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struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
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struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
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bool rfpi_enable;
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bool rfpi_enable;
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+ bool iqk_in_progress;
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u8 pwrgroup_cnt;
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u8 pwrgroup_cnt;
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u8 cck_high_power;
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u8 cck_high_power;
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@@ -1027,6 +1099,9 @@ struct rtl_phy {
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u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
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u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
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[TX_PWR_BY_RATE_NUM_RF]
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[TX_PWR_BY_RATE_NUM_RF]
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[MAX_BASE_NUM_IN_PHY_REG_PG_24G];
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[MAX_BASE_NUM_IN_PHY_REG_PG_24G];
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+ u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
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+ [TX_PWR_BY_RATE_NUM_RF]
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+ [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
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u8 default_initialgain[4];
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u8 default_initialgain[4];
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/* the current Tx power level */
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/* the current Tx power level */
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@@ -1039,6 +1114,7 @@ struct rtl_phy {
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bool apk_done;
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bool apk_done;
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u32 reg_rf3c[2]; /* pathA / pathB */
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u32 reg_rf3c[2]; /* pathA / pathB */
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+ u32 backup_rf_0x1a;/*92ee*/
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/* bfsync */
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/* bfsync */
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u8 framesync;
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u8 framesync;
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u32 framesync_c34;
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u32 framesync_c34;
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@@ -1047,6 +1123,7 @@ struct rtl_phy {
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struct phy_parameters hwparam_tables[MAX_TAB];
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struct phy_parameters hwparam_tables[MAX_TAB];
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u16 rf_pathmap;
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u16 rf_pathmap;
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+ u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
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enum rt_polarity_ctl polarity_ctl;
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enum rt_polarity_ctl polarity_ctl;
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};
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};
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@@ -1174,6 +1251,7 @@ struct rtl_mac {
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u8 use_cts_protect;
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u8 use_cts_protect;
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u8 cur_40_prime_sc;
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u8 cur_40_prime_sc;
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u8 cur_40_prime_sc_bk;
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u8 cur_40_prime_sc_bk;
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+ u8 cur_80_prime_sc;
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u64 tsf;
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u64 tsf;
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u8 retry_short;
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u8 retry_short;
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u8 retry_long;
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u8 retry_long;
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@@ -1276,6 +1354,7 @@ struct rtl_hal {
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/*Reserve page start offset except beacon in TxQ. */
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/*Reserve page start offset except beacon in TxQ. */
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u8 fw_rsvdpage_startoffset;
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u8 fw_rsvdpage_startoffset;
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u8 h2c_txcmd_seq;
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u8 h2c_txcmd_seq;
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+ u8 current_ra_rate;
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/* FW Cmd IO related */
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/* FW Cmd IO related */
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u16 fwcmd_iomap;
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u16 fwcmd_iomap;
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@@ -1315,6 +1394,9 @@ struct rtl_hal {
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bool disable_amsdu_8k;
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bool disable_amsdu_8k;
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bool master_of_dmsp;
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bool master_of_dmsp;
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bool slave_of_dmsp;
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bool slave_of_dmsp;
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+
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+ u16 rx_tag;/*for 92ee*/
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+ u8 rts_en;
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};
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};
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struct rtl_security {
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struct rtl_security {
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@@ -1412,11 +1494,18 @@ struct rtl_dm {
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u8 txpower_track_control;
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u8 txpower_track_control;
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bool interrupt_migration;
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bool interrupt_migration;
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bool disable_tx_int;
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bool disable_tx_int;
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- char ofdm_index[2];
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+ char ofdm_index[MAX_RF_PATH];
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+ u8 default_ofdm_index;
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+ u8 default_cck_index;
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char cck_index;
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char cck_index;
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char delta_power_index[MAX_RF_PATH];
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char delta_power_index[MAX_RF_PATH];
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char delta_power_index_last[MAX_RF_PATH];
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char delta_power_index_last[MAX_RF_PATH];
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char power_index_offset[MAX_RF_PATH];
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char power_index_offset[MAX_RF_PATH];
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+ char absolute_ofdm_swing_idx[MAX_RF_PATH];
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+ char remnant_ofdm_swing_idx[MAX_RF_PATH];
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+ char remnant_cck_idx;
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+ bool modify_txagc_flag_path_a;
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+ bool modify_txagc_flag_path_b;
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bool one_entry_only;
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bool one_entry_only;
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struct dm_phy_dbg_info dbginfo;
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struct dm_phy_dbg_info dbginfo;
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@@ -1431,9 +1520,10 @@ struct rtl_dm {
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u8 cfo_threshold;
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u8 cfo_threshold;
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u32 packet_count;
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u32 packet_count;
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u32 packet_count_pre;
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u32 packet_count_pre;
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+ u8 tx_rate;
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/*88e tx power tracking*/
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/*88e tx power tracking*/
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- u8 swing_idx_ofdm[2];
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+ u8 swing_idx_ofdm[MAX_RF_PATH];
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u8 swing_idx_ofdm_cur;
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u8 swing_idx_ofdm_cur;
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u8 swing_idx_ofdm_base[MAX_RF_PATH];
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u8 swing_idx_ofdm_base[MAX_RF_PATH];
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bool swing_flag_ofdm;
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bool swing_flag_ofdm;
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@@ -1442,10 +1532,43 @@ struct rtl_dm {
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u8 swing_idx_cck_base;
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u8 swing_idx_cck_base;
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bool swing_flag_cck;
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bool swing_flag_cck;
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+ char swing_diff_2g;
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+ char swing_diff_5g;
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+
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+ u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ];
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+ u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ];
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+ u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ];
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+ u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ];
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+ u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ];
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+ u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ];
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+ u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ];
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+ u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ];
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+ u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ];
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+ u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ];
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+ u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ];
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+ u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ];
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+ u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ];
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+ u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ];
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+
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/* DMSP */
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/* DMSP */
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bool supp_phymode_switch;
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bool supp_phymode_switch;
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+ /* DulMac */
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struct fast_ant_training fat_table;
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struct fast_ant_training fat_table;
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+
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+ u8 resp_tx_path;
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+ u8 path_sel;
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+ u32 patha_sum;
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+ u32 pathb_sum;
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+ u32 patha_cnt;
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+ u32 pathb_cnt;
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+
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+ u8 pre_channel;
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+ u8 *p_channel;
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+ u8 linked_interval;
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+
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+ u64 last_tx_ok_cnt;
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+ u64 last_rx_ok_cnt;
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};
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};
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#define EFUSE_MAX_LOGICAL_SIZE 256
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#define EFUSE_MAX_LOGICAL_SIZE 256
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@@ -1491,11 +1614,6 @@ struct rtl_efuse {
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u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
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u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
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u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
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u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
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u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
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u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
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- u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
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- /* For HT 40MHZ pwr */
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- u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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- u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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- u8 txpwr_ht40diff[MAX_RF_PATH][MAX_TX_COUNT];/*BW40_24G_Diff*/
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u8 internal_pa_5g[2]; /* pathA / pathB */
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u8 internal_pa_5g[2]; /* pathA / pathB */
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u8 eeprom_c9;
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u8 eeprom_c9;
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@@ -1506,9 +1624,38 @@ struct rtl_efuse {
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u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
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u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
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u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
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u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
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- char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
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- /*For HT<->legacy pwr diff*/
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- u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
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+ u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
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+ /*For HT 40MHZ pwr */
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+ u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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+ /*For HT 40MHZ pwr */
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+ u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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+
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+ /*--------------------------------------------------------*
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+ * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
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+ * other ICs (8188EE\8723BE\8192EE\8812AE...)
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+ * define new arrays in Windows code.
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+ * BUT, in linux code, we use the same array for all ICs.
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+ *
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+ * The Correspondance relation between two arrays is:
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+ * txpwr_cckdiff[][] == CCK_24G_Diff[][]
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+ * txpwr_ht20diff[][] == BW20_24G_Diff[][]
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+ * txpwr_ht40diff[][] == BW40_24G_Diff[][]
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+ * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
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+ *
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+ * Sizes of these arrays are decided by the larger ones.
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+ */
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+ char txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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+ char txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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+ char txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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+ char txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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+
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+ u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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+ u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
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+ char txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
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+ char txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
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+ char txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
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+ char txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
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+
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u8 txpwr_safetyflag; /* Band edge enable flag */
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u8 txpwr_safetyflag; /* Band edge enable flag */
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u16 eeprom_txpowerdiff;
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u16 eeprom_txpowerdiff;
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u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
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u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
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@@ -1639,7 +1786,9 @@ struct rtl_stats {
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bool rx_is40Mhzpacket;
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bool rx_is40Mhzpacket;
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u32 rx_pwdb_all;
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u32 rx_pwdb_all;
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u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
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u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
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- s8 rx_mimo_sig_qual[2];
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+ s8 rx_mimo_sig_qual[4];
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+ u8 rx_pwr[4]; /* per-path's pwdb */
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+ u8 rx_snr[4]; /* per-path's SNR */
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bool packet_matchbssid;
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bool packet_matchbssid;
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bool is_cck;
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bool is_cck;
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bool is_ht;
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bool is_ht;
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@@ -1743,9 +1892,17 @@ struct rtl_hal_ops {
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void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
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void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
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void (*update_rate_tbl) (struct ieee80211_hw *hw,
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void (*update_rate_tbl) (struct ieee80211_hw *hw,
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struct ieee80211_sta *sta, u8 rssi_level);
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struct ieee80211_sta *sta, u8 rssi_level);
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+ void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
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+ u8 *desc, u8 queue_index,
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+ struct sk_buff *skb, dma_addr_t addr);
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void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
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void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
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+ u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
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+ u8 queue_index);
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+ void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
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+ u8 queue_index);
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void (*fill_tx_desc) (struct ieee80211_hw *hw,
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void (*fill_tx_desc) (struct ieee80211_hw *hw,
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struct ieee80211_hdr *hdr, u8 *pdesc_tx,
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struct ieee80211_hdr *hdr, u8 *pdesc_tx,
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+ u8 *pbd_desc_tx,
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struct ieee80211_tx_info *info,
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struct ieee80211_tx_info *info,
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struct ieee80211_sta *sta,
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struct ieee80211_sta *sta,
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struct sk_buff *skb, u8 hw_queue,
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struct sk_buff *skb, u8 hw_queue,
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@@ -1768,7 +1925,8 @@ struct rtl_hal_ops {
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enum rf_pwrstate rfpwr_state);
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enum rf_pwrstate rfpwr_state);
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void (*led_control) (struct ieee80211_hw *hw,
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void (*led_control) (struct ieee80211_hw *hw,
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enum led_ctl_mode ledaction);
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enum led_ctl_mode ledaction);
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- void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
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+ void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
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+ u8 desc_name, u8 *val);
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u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
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u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
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bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
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bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
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u8 hw_queue, u16 index);
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u8 hw_queue, u16 index);
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@@ -1812,6 +1970,8 @@ struct rtl_hal_ops {
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u32 cmd_len, u8 *p_cmdbuffer);
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u32 cmd_len, u8 *p_cmdbuffer);
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bool (*get_btc_status) (void);
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bool (*get_btc_status) (void);
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bool (*is_fw_header) (struct rtl92c_firmware_header *hdr);
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bool (*is_fw_header) (struct rtl92c_firmware_header *hdr);
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+ u32 (*rx_command_packet)(struct ieee80211_hw *hw,
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+ struct rtl_stats status, struct sk_buff *skb);
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};
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};
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struct rtl_intf_ops {
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struct rtl_intf_ops {
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@@ -1921,6 +2081,8 @@ struct rtl_locks {
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/*Easy concurrent*/
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/*Easy concurrent*/
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spinlock_t check_sendpkt_lock;
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spinlock_t check_sendpkt_lock;
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+
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+ spinlock_t iqk_lock;
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};
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};
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struct rtl_works {
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struct rtl_works {
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@@ -2014,6 +2176,7 @@ struct dig_t {
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u8 cursta_cstate;
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u8 cursta_cstate;
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u8 presta_cstate;
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u8 presta_cstate;
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u8 curmultista_cstate;
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u8 curmultista_cstate;
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+ u8 stop_dig;
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char back_val;
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char back_val;
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char back_range_max;
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char back_range_max;
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char back_range_min;
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char back_range_min;
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@@ -2031,6 +2194,7 @@ struct dig_t {
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u8 cur_ccasate;
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u8 cur_ccasate;
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u8 large_fa_hit;
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u8 large_fa_hit;
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u8 dig_dynamic_min;
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u8 dig_dynamic_min;
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+ u8 dig_dynamic_min_1;
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u8 forbidden_igi;
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u8 forbidden_igi;
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u8 dig_state;
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u8 dig_state;
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u8 dig_highpwrstate;
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u8 dig_highpwrstate;
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@@ -2174,6 +2338,7 @@ struct rtl_priv {
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struct rtl_ps_ctl psc;
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struct rtl_ps_ctl psc;
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struct rate_adaptive ra;
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struct rate_adaptive ra;
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+ struct dynamic_primary_cca primarycca;
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struct wireless_stats stats;
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struct wireless_stats stats;
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struct rt_link_detect link_info;
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struct rt_link_detect link_info;
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struct false_alarm_statistics falsealm_cnt;
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struct false_alarm_statistics falsealm_cnt;
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@@ -2259,9 +2424,15 @@ enum bt_co_type {
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BT_CSR_BC8 = 4,
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BT_CSR_BC8 = 4,
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BT_RTL8756 = 5,
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BT_RTL8756 = 5,
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BT_RTL8723A = 6,
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BT_RTL8723A = 6,
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- BT_RTL8821 = 7,
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+ BT_RTL8821A = 7,
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BT_RTL8723B = 8,
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BT_RTL8723B = 8,
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BT_RTL8192E = 9,
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BT_RTL8192E = 9,
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+ BT_RTL8812A = 11,
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+};
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+
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+enum bt_total_ant_num {
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+ ANT_TOTAL_X2 = 0,
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+ ANT_TOTAL_X1 = 1
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};
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};
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enum bt_cur_state {
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enum bt_cur_state {
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