|
@@ -0,0 +1,60 @@
|
|
|
+Thine Electronics THC63LVD1024 LVDS decoder
|
|
|
+-------------------------------------------
|
|
|
+
|
|
|
+The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS streams
|
|
|
+to parallel data outputs. The chip supports single/dual input/output modes,
|
|
|
+handling up to two LVDS input streams and up to two digital CMOS/TTL outputs.
|
|
|
+
|
|
|
+Single or dual operation mode, output data mapping and DDR output modes are
|
|
|
+configured through input signals and the chip does not expose any control bus.
|
|
|
+
|
|
|
+Required properties:
|
|
|
+- compatible: Shall be "thine,thc63lvd1024"
|
|
|
+- vcc-supply: Power supply for TTL output, TTL CLOCKOUT signal, LVDS input,
|
|
|
+ PPL and digital circuitry
|
|
|
+
|
|
|
+Optional properties:
|
|
|
+- powerdown-gpios: Power down GPIO signal, pin name "/PDWN". Active low
|
|
|
+- oe-gpios: Output enable GPIO signal, pin name "OE". Active high
|
|
|
+
|
|
|
+The THC63LVD1024 video port connections are modeled according
|
|
|
+to OF graph bindings specified by Documentation/devicetree/bindings/graph.txt
|
|
|
+
|
|
|
+Required video port nodes:
|
|
|
+- port@0: First LVDS input port
|
|
|
+- port@2: First digital CMOS/TTL parallel output
|
|
|
+
|
|
|
+Optional video port nodes:
|
|
|
+- port@1: Second LVDS input port
|
|
|
+- port@3: Second digital CMOS/TTL parallel output
|
|
|
+
|
|
|
+Example:
|
|
|
+--------
|
|
|
+
|
|
|
+ thc63lvd1024: lvds-decoder {
|
|
|
+ compatible = "thine,thc63lvd1024";
|
|
|
+
|
|
|
+ vcc-supply = <®_lvds_vcc>;
|
|
|
+ powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
|
|
|
+
|
|
|
+ ports {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ port@0 {
|
|
|
+ reg = <0>;
|
|
|
+
|
|
|
+ lvds_dec_in_0: endpoint {
|
|
|
+ remote-endpoint = <&lvds_out>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ port@2{
|
|
|
+ reg = <2>;
|
|
|
+
|
|
|
+ lvds_dec_out_2: endpoint {
|
|
|
+ remote-endpoint = <&adv7511_in>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|